stm32f4xx/
nvic.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Named constants for NVIC ids shared across the stm32f4xx family of chips
6
7#![allow(non_upper_case_globals)]
8
9pub const WWDG: u32 = 0;
10pub const PVD: u32 = 1;
11pub const TAMP_STAMP: u32 = 2;
12pub const RTC_WKUP: u32 = 3;
13pub const FLASH: u32 = 4;
14pub const RCC: u32 = 5;
15pub const EXTI0: u32 = 6;
16pub const EXTI1: u32 = 7;
17pub const EXTI2: u32 = 8;
18pub const EXTI3: u32 = 9;
19pub const EXTI4: u32 = 10;
20pub const DMA1_Stream0: u32 = 11;
21pub const DMA1_Stream1: u32 = 12;
22pub const DMA1_Stream2: u32 = 13;
23pub const DMA1_Stream3: u32 = 14;
24pub const DMA1_Stream4: u32 = 15;
25pub const DMA1_Stream5: u32 = 16;
26pub const DMA1_Stream6: u32 = 17;
27pub const ADC: u32 = 18;
28pub const CAN1_TX: u32 = 19;
29pub const CAN1_RX0: u32 = 20;
30pub const CAN1_RX1: u32 = 21;
31pub const CAN1_SCE: u32 = 22;
32pub const EXTI9_5: u32 = 23;
33pub const TIM1_BRK_TIM9: u32 = 24;
34pub const TIM1_UP_TIM10: u32 = 25;
35pub const TIM1_TRG_COM_TIM11: u32 = 26;
36pub const TIM1_CC: u32 = 27;
37pub const TIM2: u32 = 28;
38pub const TIM3: u32 = 29;
39pub const TIM4: u32 = 30;
40pub const I2C1_EV: u32 = 31;
41pub const I2C1_ER: u32 = 32;
42pub const I2C2_EV: u32 = 33;
43pub const I2C2_ER: u32 = 34;
44pub const SPI1: u32 = 35;
45pub const SPI2: u32 = 36;
46pub const USART1: u32 = 37;
47pub const USART2: u32 = 38;
48pub const USART3: u32 = 39;
49pub const EXTI15_10: u32 = 40;
50pub const RTC_Alarm: u32 = 41;
51pub const OTG_FS_WKUP: u32 = 42;
52pub const TIM8_BRK_TIM12: u32 = 43;
53pub const TIM8_UP_TIM13: u32 = 44;
54pub const TIM8_TRG_COM_TIM14: u32 = 45;
55pub const TIM8_CC: u32 = 46;
56pub const DMA1_Stream7: u32 = 47;
57pub const FMC: u32 = 48;
58pub const SDIO: u32 = 49;
59pub const TIM5: u32 = 50;
60pub const SPI3: u32 = 51;
61pub const UART4: u32 = 52;
62pub const UART5: u32 = 53;
63pub const TIM6_DAC: u32 = 54;
64pub const TIM7: u32 = 55;
65pub const DMA2_Stream0: u32 = 56;
66pub const DMA2_Stream1: u32 = 57;
67pub const DMA2_Stream2: u32 = 58;
68pub const DMA2_Stream3: u32 = 59;
69pub const DMA2_Stream4: u32 = 60;
70pub const CAN2_TX: u32 = 63;
71pub const CAN2_RX0: u32 = 64;
72pub const CAN2_RX1: u32 = 65;
73pub const CAN2_SCE: u32 = 66;
74pub const OTG_FS: u32 = 67;
75pub const DMA2_Stream5: u32 = 68;
76pub const DMA2_Stream6: u32 = 69;
77pub const DMA2_Stream7: u32 = 70;
78pub const USART6: u32 = 71;
79pub const I2C3_EV: u32 = 72;
80pub const I2C3_ER: u32 = 73;
81pub const OTG_HS_EP1_OUT: u32 = 74;
82pub const OTG_HS_EP1_IN: u32 = 75;
83pub const OTG_HS_WKUP: u32 = 76;
84pub const OTG_HS: u32 = 77;
85pub const DCMI: u32 = 78;
86pub const FPU: u32 = 81;
87pub const SPI4: u32 = 84;
88pub const SAI1: u32 = 87;
stm32f4xx/nvic.rs

stm32f4xx/
nvic.rs
