rp2040/
uart.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5use core::cell::Cell;
6use kernel::deferred_call::{DeferredCall, DeferredCallClient};
7use kernel::hil;
8use kernel::hil::uart::ReceiveClient;
9use kernel::hil::uart::{
10    Configure, Parameters, Parity, Receive, StopBits, Transmit, TransmitClient, Width,
11};
12use kernel::utilities::cells::{OptionalCell, TakeCell};
13use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable};
14use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite};
15use kernel::utilities::StaticRef;
16use kernel::ErrorCode;
17
18use crate::clocks;
19
20register_structs! {
21    /// controls serial port
22    UartRegisters {
23        (0x000 => uartdr: ReadWrite<u32, UARTDR::Register>),
24
25        (0x004 => uartrsr: ReadWrite<u32, UARTRSR::Register>),
26        (0x008 => _reserved0),
27
28        (0x018 => uartfr: ReadOnly<u32, UARTFR::Register>),
29        (0x01c => _reserved1),
30
31        (0x020 => uartilpr: ReadWrite<u32, UARTILPR::Register>),
32
33        (0x024 => uartibrd: ReadWrite<u32, UARTIBRD::Register>),
34
35        (0x028 => uartfbrd: ReadWrite<u32, UARTFBRD::Register>),
36
37        (0x02c => uartlcr_h: ReadWrite<u32, UARTLCR_H::Register>),
38
39        (0x030 => uartcr: ReadWrite<u32, UARTCR::Register>),
40
41        (0x034 => uartifls: ReadWrite<u32, UARTIFLS::Register>),
42
43        (0x038 => uartimsc: ReadWrite<u32, UARTIMSC::Register>),
44
45        (0x03c => uartris: ReadOnly<u32, UARTRIS::Register>),
46
47        (0x040 => uartmis: ReadOnly<u32, UARTMIS::Register>),
48
49        (0x044 => uarticr: ReadWrite<u32, UARTICR::Register>),
50
51        (0x048 => uartdmacr: ReadWrite<u32, UARTDMACR::Register>),
52        (0x04c => _reserved2),
53
54        (0xfe0 => uartperiphid0: ReadOnly<u32, UARTPERIPHID0::Register>),
55
56        (0xfe4 => uartperiphid1: ReadOnly<u32, UARTPERIPHID1::Register>),
57
58        (0xfe8 => uartperiphid2: ReadOnly<u32, UARTPERIPHID2::Register>),
59
60        (0xfec => uartperiphid3: ReadOnly<u32, UARTPERIPHID3::Register>),
61
62        (0xff0 => uartpcellid0: ReadOnly<u32, UARTPCELLID0::Register>),
63
64        (0xff4 => uartpcellid1: ReadOnly<u32, UARTPCELLID1::Register>),
65
66        (0xff8 => uartpcellid2: ReadOnly<u32, UARTPCELLID2::Register>),
67
68        (0xffc => uartpcellid3: ReadOnly<u32, UARTPCELLID3::Register>),
69
70        (0x1000 => @END),
71    }
72}
73
74register_bitfields! [u32,
75    /// data register
76    UARTDR [
77        /// data bytes
78        DATA OFFSET(0) NUMBITS(8) [],
79        /// framing error
80        FE OFFSET(8) NUMBITS(1) [],
81        /// parity error
82        PE OFFSET(9) NUMBITS(1) [],
83        /// break error
84        BE OFFSET(10) NUMBITS(1) [],
85        /// overrun error
86        OE OFFSET(11) NUMBITS(1) []
87    ],
88    /// receive status register/ error clear register
89    UARTRSR [
90        /// framing error
91        FE OFFSET(0) NUMBITS(1) [],
92        /// parity error
93        PE OFFSET(1) NUMBITS(1) [],
94        /// break error
95        BE OFFSET(2) NUMBITS(1) [],
96        /// overrun error
97        OE OFFSET(3) NUMBITS(1) []
98    ],
99    /// flag register
100    UARTFR  [
101        /// clear to send
102        CTS OFFSET(0) NUMBITS(1) [],
103        /// data set ready
104        DSR OFFSET(1) NUMBITS(1) [],
105        /// data carrier detect
106        DCD OFFSET(2) NUMBITS(1) [],
107        /// busy
108        BUSY OFFSET(3) NUMBITS(1) [],
109        /// receive FIFO empty
110        RXFE OFFSET(4) NUMBITS(1) [],
111        /// transmit FIFO full
112        TXFF OFFSET(5) NUMBITS(1) [],
113        /// receive FIFO full
114        RXFF OFFSET(6) NUMBITS(1) [],
115        /// transmit FIFO empty
116        TXFE OFFSET(7) NUMBITS(1) [],
117        /// ring indicator
118        RI OFFSET(8) NUMBITS(1) []
119    ],
120    /// IrDA low-power counter register
121    UARTILPR [
122        /// 8-bit low-power divisor value
123        ILPDVSR OFFSET(0) NUMBITS(8) []
124    ],
125    /// integer baud rate register
126    UARTIBRD [
127        /// the integer baud rate divisor
128        BAUD_DIVINT OFFSET(0) NUMBITS(16) []
129    ],
130    /// fractional baud rate register
131    UARTFBRD [
132        /// the fractional baud rate divisor
133        BAUD_DIVFRAC OFFSET(0) NUMBITS(6) []
134    ],
135    /// line control register
136    UARTLCR_H [
137        /// send break
138        BRK OFFSET(0) NUMBITS(1) [],
139        /// parity enable
140        PEN OFFSET(1) NUMBITS(1) [],
141        /// even parity select
142        EPS OFFSET(2) NUMBITS(1) [],
143        /// two stop bits select
144        STP2 OFFSET(3) NUMBITS(1) [],
145        /// enable FIFOs
146        FEN OFFSET(4) NUMBITS(1) [],
147        /// word length
148        WLEN OFFSET(5) NUMBITS(2) [
149            BITS_8 = 0b11,
150            BITS_7 = 0b10,
151            BITS_6 = 0b01,
152            BITS_5 = 0b00
153        ],
154        /// stick parity select
155        SPS OFFSET(7) NUMBITS(1) []
156    ],
157    /// control register
158    UARTCR [
159        /// UART enable
160        UARTEN OFFSET(0) NUMBITS(1) [],
161        /// SIR enable
162        SIREN OFFSET(1) NUMBITS(1) [],
163        /// SIR low-power IrDA mode
164        SIRLP OFFSET(2) NUMBITS(1) [],
165
166        //RESERVED OFFSET(3) NUMBITS(3) [],
167        /// loopback enable
168        LBE OFFSET(7) NUMBITS(1) [],
169        /// transmit enable
170        TXE OFFSET(8) NUMBITS(1) [],
171        /// receive enable
172        RXE OFFSET(9) NUMBITS(1) [],
173        /// data transmit ready
174        DTR OFFSET(10) NUMBITS(1) [],
175        /// request to send
176        RTS OFFSET(11) NUMBITS(1) [],
177        /// the complement of the UART Out1 (nUARTOut1) modem status output
178        OUT1 OFFSET(12) NUMBITS(1) [],
179        /// the complement of the UART Out2 (nUARTOut2) modem status output
180        OUT2 OFFSET(13) NUMBITS(1) [],
181        /// RTS hardware flow control enable
182        RTSEN OFFSET(14) NUMBITS(1) [],
183        /// CTS hardware flow control enable
184        CTSEN OFFSET(15) NUMBITS(1) []
185    ],
186    /// interrupt FIFO level select register
187    UARTIFLS [
188        /// transmit interrupt FIFO level select
189        TXIFLSEL OFFSET(0) NUMBITS(3) [
190            FIFO_1_8 = 0b000,
191            FIFO_1_4 = 0b001,
192            FIFO_1_2 = 0b010,
193            FIFO_3_4 = 0b011,
194            FIFO_7_8 = 0b100,
195        ],
196        /// receive interrupt FIFO level select
197        RXIFLSEL OFFSET(3) NUMBITS(3) [
198            FIFO_1_8 = 0b000,
199            FIFO_1_4 = 0b001,
200            FIFO_1_2 = 0b010,
201            FIFO_3_4 = 0b011,
202            FIFO_7_8 = 0b100,
203        ]
204    ],
205
206    /// interrupt mask set/clear register
207    UARTIMSC [
208        /// nUARTRI modem interrupt mask
209        RIMIM OFFSET(0) NUMBITS(1) [],
210        /// nUARTCTS modem interrupt mask
211        CTSMIM OFFSET(1) NUMBITS(1) [],
212        /// nUARTDCD modem interrupt mask
213        DCDMIM OFFSET(2) NUMBITS(1) [],
214        /// nUARTDSR modem interrupt mask
215        DSRMIM OFFSET(3) NUMBITS(1) [],
216        /// receive interrupt mask
217        RXIM OFFSET(4) NUMBITS(1) [],
218        /// transmit interrupt mask
219        TXIM OFFSET(5) NUMBITS(1) [],
220        /// receive timeout interrupt mask
221        RTIM OFFSET(6) NUMBITS(1) [],
222        /// framing error interrupt mask
223        FEIM OFFSET(7) NUMBITS(1) [],
224        /// parity error interrupt mask
225        PEIM OFFSET(8) NUMBITS(1) [],
226        /// break error interrupt mask
227        BEIM OFFSET(9) NUMBITS(1) [],
228        /// overrun error interrupt mask
229        OEIM OFFSET(10) NUMBITS(1) []
230    ],
231    /// raw interrupt status register
232    UARTRIS [
233        /// nUARTRI modem interrupt status
234        RIRMIS OFFSET(0) NUMBITS(1) [],
235        /// nUARTCTS modem interrupt status
236        CTSRMIS OFFSET(1) NUMBITS(1) [],
237        /// nUARTDCD modem interrupt status
238        DCDRMIS OFFSET(2) NUMBITS(1) [],
239        /// nUARTDSR modem interrupt status
240        DSRRMIS OFFSET(3) NUMBITS(1) [],
241        /// receive interrupt status
242        RXRIS OFFSET(4) NUMBITS(1) [],
243        /// transmit interrupt status
244        TXRIS OFFSET(5) NUMBITS(1) [],
245        /// receive timeout interrupt status
246        RTRIS OFFSET(6) NUMBITS(1) [],
247        /// framing error interrupt status
248        FERIS OFFSET(7) NUMBITS(1) [],
249        /// parity error interrupt status
250        PERIS OFFSET(8) NUMBITS(1) [],
251        /// break error interrupt status
252        BERIS OFFSET(9) NUMBITS(1) [],
253        /// overrun error interrupt status
254        OERIS OFFSET(10) NUMBITS(1) []
255    ],
256    /// masked interrupt status register
257    UARTMIS [
258        /// nUARTRI modem masked interrupt status
259        RIMMIS OFFSET(0) NUMBITS(1) [],
260        /// nUARTCTS modem masked interrupt status
261        CTSMMIS OFFSET(1) NUMBITS(1) [],
262        /// nUARTDCD modem masked interrupt status
263        DCDMMIS OFFSET(2) NUMBITS(1) [],
264        /// nUARTDSR modem masked interrupt status
265        DSRMMIS OFFSET(3) NUMBITS(1) [],
266        /// receive masked interrupt status
267        RXMIS OFFSET(4) NUMBITS(1) [],
268        /// transmit masked interrupt status
269        TXMIS OFFSET(5) NUMBITS(1) [],
270        /// receive timeout masked interrupt status
271        RTMIS OFFSET(6) NUMBITS(1) [],
272        /// framing error masked interrupt status
273        FEMIS OFFSET(7) NUMBITS(1) [],
274        /// parity error masked interrupt status
275        PEMIS OFFSET(8) NUMBITS(1) [],
276        /// break error masked interrupt status
277        BEMIS OFFSET(9) NUMBITS(1) [],
278        /// overrun error masked interrupt status
279        OEMIS OFFSET(10) NUMBITS(1) []
280    ],
281    /// interrupt clear register
282    UARTICR [
283        /// nUARTRI modem interrupt clear
284        RIMIC OFFSET(0) NUMBITS(1) [],
285        /// nUARTCTS modem interrupt clear
286        CTSMIC OFFSET(1) NUMBITS(1) [],
287        /// nUARTDCD modem interrupt clear
288        DCDMIC OFFSET(2) NUMBITS(1) [],
289        /// nUARTDSR modem interrupt clear
290        DSRMIC OFFSET(3) NUMBITS(1) [],
291        /// receive interrupt clear
292        RXIC OFFSET(4) NUMBITS(1) [],
293        /// transmit interrupt clear
294        TXIC OFFSET(5) NUMBITS(1) [],
295        /// receive timeout interrupt clear
296        RTIC OFFSET(6) NUMBITS(1) [],
297        /// framing error interrupt clear
298        FEIC OFFSET(7) NUMBITS(1) [],
299        /// parity error interrupt clear
300        PEIC OFFSET(8) NUMBITS(1) [],
301        /// break error interrupt clear
302        BEIC OFFSET(9) NUMBITS(1) [],
303        /// overrun error interrupt clear
304        OEIC OFFSET(10) NUMBITS(1) []
305    ],
306    /// DMA control register
307    UARTDMACR [
308        /// Receive DMA enable
309        RXDMAE OFFSET(0) NUMBITS(1) [],
310        /// transmit DMA enable
311        TXDMAE OFFSET(1) NUMBITS(1) [],
312        /// DMA on error
313        DMAONERR OFFSET(2) NUMBITS(1) []
314    ],
315    /// UARTPeriphID0 register
316    UARTPERIPHID0 [
317        /// these bits read back as 0x11
318        PARTNUMBER0 OFFSET(0) NUMBITS(8) []
319    ],
320    /// UARTPeriphID1 register
321    UARTPERIPHID1 [
322        /// these bits read back as 0x0
323        PARTNUMBER1 OFFSET(0) NUMBITS(4) [],
324        /// these bits read back as 0x1
325        DESIGNER0 OFFSET(4) NUMBITS(4) []
326    ],
327    /// UARTPeriphID2 register
328    UARTPERIPHID2 [
329        /// these bits read back as 0x4
330        DESIGNER1 OFFSET(0) NUMBITS(4) [],
331        /// this field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3
332        REVISION OFFSET(4) NUMBITS(4) []
333    ],
334    /// UARTPeriphID3 register
335    UARTPERIPHID3 [
336        /// these bits read back as 0x00
337        CONFIGURATION OFFSET(0) NUMBITS(8) []
338    ],
339    /// UARTPCellID0 register
340    UARTPCELLID0 [
341        /// these bits read back as 0x0D
342        UARTPCELLID0 OFFSET(0) NUMBITS(8) []
343    ],
344    /// UARTPCellID1 register
345    UARTPCELLID1 [
346        /// these bits read back as 0xF0
347        UARTPCELLID1 OFFSET(0) NUMBITS(8) []
348    ],
349    /// UARTPCellID2 register
350    UARTPCELLID2 [
351        /// these bits read back as 0x05
352        UARTPCELLID2 OFFSET(0) NUMBITS(8) []
353    ],
354    /// UARTPCellID3 register
355    UARTPCELLID3 [
356        /// these bits read back as 0xB1
357        UARTPCELLID3 OFFSET(0) NUMBITS(8) []
358    ]
359];
360
361#[derive(Copy, Clone, PartialEq)]
362enum UARTStateTX {
363    Idle,
364    Transmitting,
365    AbortRequested,
366}
367
368#[derive(Copy, Clone, PartialEq)]
369enum UARTStateRX {
370    Idle,
371    Receiving,
372    AbortRequested,
373}
374
375const UART0_BASE: StaticRef<UartRegisters> =
376    unsafe { StaticRef::new(0x40034000 as *const UartRegisters) };
377
378const UART1_BASE: StaticRef<UartRegisters> =
379    unsafe { StaticRef::new(0x40038000 as *const UartRegisters) };
380
381pub struct Uart<'a> {
382    registers: StaticRef<UartRegisters>,
383    clocks: OptionalCell<&'a clocks::Clocks>,
384
385    tx_client: OptionalCell<&'a dyn TransmitClient>,
386    rx_client: OptionalCell<&'a dyn ReceiveClient>,
387
388    tx_buffer: TakeCell<'static, [u8]>,
389    tx_position: Cell<usize>,
390    tx_len: Cell<usize>,
391    tx_status: Cell<UARTStateTX>,
392
393    rx_buffer: TakeCell<'static, [u8]>,
394    rx_position: Cell<usize>,
395    rx_len: Cell<usize>,
396    rx_status: Cell<UARTStateRX>,
397
398    deferred_call: DeferredCall,
399}
400
401impl<'a> Uart<'a> {
402    pub fn new_uart0() -> Self {
403        Self {
404            registers: UART0_BASE,
405            clocks: OptionalCell::empty(),
406
407            tx_client: OptionalCell::empty(),
408            rx_client: OptionalCell::empty(),
409
410            tx_buffer: TakeCell::empty(),
411            tx_position: Cell::new(0),
412            tx_len: Cell::new(0),
413            tx_status: Cell::new(UARTStateTX::Idle),
414
415            rx_buffer: TakeCell::empty(),
416            rx_position: Cell::new(0),
417            rx_len: Cell::new(0),
418            rx_status: Cell::new(UARTStateRX::Idle),
419
420            deferred_call: DeferredCall::new(),
421        }
422    }
423    pub fn new_uart1() -> Self {
424        Self {
425            registers: UART1_BASE,
426            clocks: OptionalCell::empty(),
427
428            tx_client: OptionalCell::empty(),
429            rx_client: OptionalCell::empty(),
430
431            tx_buffer: TakeCell::empty(),
432            tx_position: Cell::new(0),
433            tx_len: Cell::new(0),
434            tx_status: Cell::new(UARTStateTX::Idle),
435            rx_buffer: TakeCell::empty(),
436            rx_position: Cell::new(0),
437            rx_len: Cell::new(0),
438            rx_status: Cell::new(UARTStateRX::Idle),
439
440            deferred_call: DeferredCall::new(),
441        }
442    }
443
444    pub(crate) fn set_clocks(&self, clocks: &'a clocks::Clocks) {
445        self.clocks.set(clocks);
446    }
447
448    pub fn enable(&self) {
449        self.registers.uartcr.modify(UARTCR::UARTEN::SET);
450    }
451
452    pub fn disable(&self) {
453        self.registers.uartcr.modify(UARTCR::UARTEN::CLEAR);
454    }
455
456    pub fn enable_transmit_interrupt(&self) {
457        self.registers.uartimsc.modify(UARTIMSC::TXIM::SET);
458    }
459
460    pub fn disable_transmit_interrupt(&self) {
461        self.registers.uartimsc.modify(UARTIMSC::TXIM::CLEAR);
462    }
463
464    pub fn enable_receive_interrupt(&self) {
465        self.registers.uartifls.modify(UARTIFLS::RXIFLSEL::FIFO_1_8);
466
467        self.registers.uartimsc.modify(UARTIMSC::RXIM::SET);
468    }
469
470    pub fn disable_receive_interrupt(&self) {
471        self.registers.uartimsc.modify(UARTIMSC::RXIM::CLEAR);
472    }
473
474    fn uart_is_writable(&self) -> bool {
475        !self.registers.uartfr.is_set(UARTFR::TXFF)
476    }
477
478    pub fn send_byte(&self, data: u8) {
479        while !self.uart_is_writable() {}
480        self.registers.uartdr.write(UARTDR::DATA.val(data as u32));
481    }
482
483    pub fn handle_interrupt(&self) {
484        if self.registers.uartimsc.is_set(UARTIMSC::TXIM) {
485            if self.registers.uartfr.is_set(UARTFR::TXFE) {
486                if self.tx_status.get() == UARTStateTX::Idle {
487                    panic!("No data to transmit");
488                } else if self.tx_status.get() == UARTStateTX::Transmitting {
489                    self.disable_transmit_interrupt();
490                    if self.tx_position.get() < self.tx_len.get() {
491                        self.fill_fifo();
492                        self.enable_transmit_interrupt();
493                    }
494                    // Transmission is done
495                    else {
496                        self.tx_status.set(UARTStateTX::Idle);
497                        self.tx_client.map(|client| {
498                            self.tx_buffer.take().map(|buf| {
499                                client.transmitted_buffer(buf, self.tx_position.get(), Ok(()));
500                            });
501                        });
502                    }
503                }
504            }
505        }
506
507        if self.registers.uartimsc.is_set(UARTIMSC::RXIM) {
508            if self.registers.uartfr.is_set(UARTFR::RXFF) {
509                let byte = self.registers.uartdr.get() as u8;
510
511                self.disable_receive_interrupt();
512                if self.rx_status.get() == UARTStateRX::Receiving {
513                    if self.rx_position.get() < self.rx_len.get() {
514                        self.rx_buffer.map(|buf| {
515                            buf[self.rx_position.get()] = byte;
516                            self.rx_position.replace(self.rx_position.get() + 1);
517                        });
518                    }
519                    if self.rx_position.get() == self.rx_len.get() {
520                        // reception done
521                        self.rx_status.replace(UARTStateRX::Idle);
522                    } else {
523                        self.enable_receive_interrupt();
524                    }
525                    // notify client if transfer is done
526                    if self.rx_status.get() == UARTStateRX::Idle {
527                        self.rx_client.map(|client| {
528                            if let Some(buf) = self.rx_buffer.take() {
529                                client.received_buffer(
530                                    buf,
531                                    self.rx_len.get(),
532                                    Ok(()),
533                                    hil::uart::Error::None,
534                                );
535                            }
536                        });
537                    }
538                }
539            }
540        }
541    }
542
543    fn fill_fifo(&self) {
544        while self.uart_is_writable() && self.tx_position.get() < self.tx_len.get() {
545            self.tx_buffer.map(|buf| {
546                self.registers
547                    .uartdr
548                    .set(buf[self.tx_position.get()].into());
549                self.tx_position.replace(self.tx_position.get() + 1);
550            });
551        }
552    }
553
554    pub fn is_configured(&self) -> bool {
555        self.registers.uartcr.is_set(UARTCR::UARTEN)
556            && (self.registers.uartcr.is_set(UARTCR::RXE)
557                || self.registers.uartcr.is_set(UARTCR::TXE))
558    }
559}
560
561impl DeferredCallClient for Uart<'_> {
562    fn register(&'static self) {
563        self.deferred_call.register(self)
564    }
565
566    fn handle_deferred_call(&self) {
567        if self.tx_status.get() == UARTStateTX::AbortRequested {
568            // alert client
569            self.tx_client.map(|client| {
570                self.tx_buffer.take().map(|buf| {
571                    client.transmitted_buffer(buf, self.tx_position.get(), Err(ErrorCode::CANCEL));
572                });
573            });
574            self.tx_status.set(UARTStateTX::Idle);
575        }
576
577        if self.rx_status.get() == UARTStateRX::AbortRequested {
578            // alert client
579            self.rx_client.map(|client| {
580                self.rx_buffer.take().map(|buf| {
581                    client.received_buffer(
582                        buf,
583                        self.rx_position.get(),
584                        Err(ErrorCode::CANCEL),
585                        hil::uart::Error::Aborted,
586                    );
587                });
588            });
589            self.rx_status.set(UARTStateRX::Idle);
590        }
591    }
592}
593
594impl Configure for Uart<'_> {
595    fn configure(&self, params: Parameters) -> Result<(), ErrorCode> {
596        self.disable();
597        self.registers.uartlcr_h.modify(UARTLCR_H::FEN::CLEAR);
598
599        let clk = self.clocks.map_or(125_000_000, |clocks| {
600            clocks.get_frequency(clocks::Clock::Peripheral)
601        });
602
603        // Calculate baud rate
604        let baud_rate_div = 8 * clk / params.baud_rate;
605        let mut baud_ibrd = baud_rate_div >> 7;
606        let mut baud_fbrd = (baud_rate_div & 0x7f).div_ceil(2);
607
608        if baud_ibrd == 0 {
609            baud_ibrd = 1;
610            baud_fbrd = 0;
611        } else if baud_ibrd >= 65535 {
612            baud_ibrd = 65535;
613            baud_fbrd = 0;
614        }
615
616        self.registers
617            .uartibrd
618            .write(UARTIBRD::BAUD_DIVINT.val(baud_ibrd));
619        self.registers
620            .uartfbrd
621            .write(UARTFBRD::BAUD_DIVFRAC.val(baud_fbrd));
622
623        self.registers.uartlcr_h.modify(UARTLCR_H::BRK::SET);
624        // Configure the word length
625        match params.width {
626            Width::Six => self.registers.uartlcr_h.modify(UARTLCR_H::WLEN::BITS_6),
627            Width::Seven => self.registers.uartlcr_h.modify(UARTLCR_H::WLEN::BITS_7),
628            Width::Eight => self.registers.uartlcr_h.modify(UARTLCR_H::WLEN::BITS_8),
629        }
630
631        // Configure parity
632        match params.parity {
633            Parity::None => {
634                self.registers.uartlcr_h.modify(UARTLCR_H::PEN::CLEAR);
635                self.registers.uartlcr_h.modify(UARTLCR_H::EPS::CLEAR);
636            }
637
638            Parity::Odd => {
639                self.registers.uartlcr_h.modify(UARTLCR_H::PEN::SET);
640                self.registers.uartlcr_h.modify(UARTLCR_H::EPS::CLEAR);
641            }
642            Parity::Even => {
643                self.registers.uartlcr_h.modify(UARTLCR_H::PEN::SET);
644                self.registers.uartlcr_h.modify(UARTLCR_H::EPS::SET);
645            }
646        }
647
648        // Set the stop bit length - 2 stop bits
649        match params.stop_bits {
650            StopBits::One => self.registers.uartlcr_h.modify(UARTLCR_H::STP2::CLEAR),
651            StopBits::Two => self.registers.uartlcr_h.modify(UARTLCR_H::STP2::SET),
652        }
653
654        // Set flow control
655        if params.hw_flow_control {
656            self.registers.uartcr.modify(UARTCR::RTSEN::SET);
657            self.registers.uartcr.modify(UARTCR::CTSEN::SET);
658        } else {
659            self.registers.uartcr.modify(UARTCR::RTSEN::CLEAR);
660            self.registers.uartcr.modify(UARTCR::CTSEN::CLEAR);
661        }
662        self.registers.uartlcr_h.modify(UARTLCR_H::BRK::CLEAR);
663
664        // FIFO is not precise enough for receive
665        self.registers.uartlcr_h.modify(UARTLCR_H::FEN::CLEAR);
666
667        // Enable uart and transmit
668        self.registers
669            .uartcr
670            .modify(UARTCR::UARTEN::SET + UARTCR::TXE::SET + UARTCR::RXE::SET);
671
672        self.registers
673            .uartdmacr
674            .write(UARTDMACR::TXDMAE::SET + UARTDMACR::RXDMAE::SET);
675
676        Ok(())
677    }
678}
679
680impl<'a> Transmit<'a> for Uart<'a> {
681    fn set_transmit_client(&self, client: &'a dyn TransmitClient) {
682        self.tx_client.set(client);
683    }
684
685    fn transmit_buffer(
686        &self,
687        tx_buffer: &'static mut [u8],
688        tx_len: usize,
689    ) -> Result<(), (ErrorCode, &'static mut [u8])> {
690        if self.tx_status.get() == UARTStateTX::Idle {
691            if tx_len <= tx_buffer.len() {
692                self.tx_buffer.put(Some(tx_buffer));
693                self.tx_position.set(0);
694                self.tx_len.set(tx_len);
695                self.tx_status.set(UARTStateTX::Transmitting);
696                self.enable_transmit_interrupt();
697                self.fill_fifo();
698                Ok(())
699            } else {
700                Err((ErrorCode::SIZE, tx_buffer))
701            }
702        } else {
703            Err((ErrorCode::BUSY, tx_buffer))
704        }
705    }
706
707    fn transmit_word(&self, _word: u32) -> Result<(), ErrorCode> {
708        Err(ErrorCode::FAIL)
709    }
710
711    fn transmit_abort(&self) -> Result<(), ErrorCode> {
712        if self.tx_status.get() != UARTStateTX::Idle {
713            self.disable_transmit_interrupt();
714            self.tx_status.set(UARTStateTX::AbortRequested);
715
716            self.deferred_call.set();
717
718            Err(ErrorCode::BUSY)
719        } else {
720            Ok(())
721        }
722    }
723}
724
725impl<'a> Receive<'a> for Uart<'a> {
726    fn set_receive_client(&self, client: &'a dyn ReceiveClient) {
727        self.rx_client.set(client);
728    }
729
730    fn receive_buffer(
731        &self,
732        rx_buffer: &'static mut [u8],
733        rx_len: usize,
734    ) -> Result<(), (ErrorCode, &'static mut [u8])> {
735        if self.rx_status.get() == UARTStateRX::Idle {
736            if rx_len <= rx_buffer.len() {
737                self.rx_buffer.put(Some(rx_buffer));
738                self.rx_position.set(0);
739                self.rx_len.set(rx_len);
740                self.rx_status.set(UARTStateRX::Receiving);
741                self.enable_receive_interrupt();
742                Ok(())
743            } else {
744                Err((ErrorCode::SIZE, rx_buffer))
745            }
746        } else {
747            Err((ErrorCode::BUSY, rx_buffer))
748        }
749    }
750
751    fn receive_word(&self) -> Result<(), ErrorCode> {
752        Err(ErrorCode::FAIL)
753    }
754
755    fn receive_abort(&self) -> Result<(), ErrorCode> {
756        if self.rx_status.get() != UARTStateRX::Idle {
757            self.disable_receive_interrupt();
758            self.rx_status.set(UARTStateRX::AbortRequested);
759
760            self.deferred_call.set();
761
762            Err(ErrorCode::BUSY)
763        } else {
764            Ok(())
765        }
766    }
767}
rp2040/uart.rs

rp2040/
uart.rs
