rp2040/
chip.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Chip trait setup.
6
7use core::fmt::Write;
8use kernel::platform::chip::Chip;
9use kernel::platform::chip::InterruptService;
10
11use crate::adc;
12use crate::clocks::Clocks;
13use crate::gpio::{RPGpio, RPPins, SIO};
14use crate::i2c;
15use crate::interrupts;
16use crate::pio::Pio;
17use crate::pwm;
18use crate::resets::Resets;
19use crate::rtc;
20use crate::spi;
21use crate::sysinfo;
22use crate::timer::RPTimer;
23use crate::uart::Uart;
24use crate::usb;
25use crate::watchdog::Watchdog;
26use crate::xosc::Xosc;
27use cortexm0p::{interrupt_mask, CortexM0P, CortexMVariant};
28
29#[repr(u8)]
30pub enum Processor {
31    Processor0 = 0,
32    Processor1 = 1,
33}
34
35pub struct Rp2040<'a, I: InterruptService + 'a> {
36    mpu: cortexm0p::mpu::MPU,
37    userspace_kernel_boundary: cortexm0p::syscall::SysCall,
38    interrupt_service: &'a I,
39    sio: &'a SIO,
40    processor0_interrupt_mask: (u128, u128),
41    processor1_interrupt_mask: (u128, u128),
42}
43
44impl<'a, I: InterruptService> Rp2040<'a, I> {
45    pub unsafe fn new(interrupt_service: &'a I, sio: &'a SIO) -> Self {
46        Self {
47            mpu: cortexm0p::mpu::MPU::new(),
48            userspace_kernel_boundary: cortexm0p::syscall::SysCall::new(),
49            interrupt_service,
50            sio,
51            processor0_interrupt_mask: interrupt_mask!(interrupts::SIO_IRQ_PROC1),
52            processor1_interrupt_mask: interrupt_mask!(interrupts::SIO_IRQ_PROC0),
53        }
54    }
55}
56
57impl<I: InterruptService> Chip for Rp2040<'_, I> {
58    type MPU = cortexm0p::mpu::MPU;
59    type UserspaceKernelBoundary = cortexm0p::syscall::SysCall;
60
61    fn service_pending_interrupts(&self) {
62        unsafe {
63            let mask = match self.sio.get_processor() {
64                Processor::Processor0 => self.processor0_interrupt_mask,
65                Processor::Processor1 => self.processor1_interrupt_mask,
66            };
67            loop {
68                if let Some(interrupt) = cortexm0p::nvic::next_pending_with_mask(mask) {
69                    // ignore SIO_IRQ_PROC1 as it is intended for processor 1
70                    // not able to unset its pending status
71                    // probably only processor 1 can unset the pending by reading the fifo
72                    if !self.interrupt_service.service_interrupt(interrupt) {
73                        panic!("unhandled interrupt {}", interrupt);
74                    }
75                    let n = cortexm0p::nvic::Nvic::new(interrupt);
76                    n.clear_pending();
77                    n.enable();
78                } else {
79                    break;
80                }
81            }
82        }
83    }
84
85    fn has_pending_interrupts(&self) -> bool {
86        // ignore SIO_IRQ_PROC1 as it is intended for processor 1
87        // not able to unset its pending status
88        // probably only processor 1 can unset the pending by reading the fifo
89        let mask = match self.sio.get_processor() {
90            Processor::Processor0 => self.processor0_interrupt_mask,
91            Processor::Processor1 => self.processor1_interrupt_mask,
92        };
93        unsafe { cortexm0p::nvic::has_pending_with_mask(mask) }
94    }
95
96    fn mpu(&self) -> &Self::MPU {
97        &self.mpu
98    }
99
100    fn userspace_kernel_boundary(&self) -> &Self::UserspaceKernelBoundary {
101        &self.userspace_kernel_boundary
102    }
103
104    fn sleep(&self) {
105        unsafe {
106            cortexm0p::support::wfi();
107        }
108    }
109
110    unsafe fn atomic<F, R>(&self, f: F) -> R
111    where
112        F: FnOnce() -> R,
113    {
114        cortexm0p::support::atomic(f)
115    }
116
117    unsafe fn print_state(&self, writer: &mut dyn Write) {
118        CortexM0P::print_cortexm_state(writer);
119    }
120}
121
122pub struct Rp2040DefaultPeripherals<'a> {
123    pub adc: adc::Adc<'a>,
124    pub clocks: Clocks,
125    pub i2c0: i2c::I2c<'a, 'a>,
126    pub pins: RPPins<'a>,
127    pub pio0: Pio,
128    pub pio1: Pio,
129    pub pwm: pwm::Pwm<'a>,
130    pub resets: Resets,
131    pub sio: SIO,
132    pub spi0: spi::Spi<'a>,
133    pub sysinfo: sysinfo::SysInfo,
134    pub timer: RPTimer<'a>,
135    pub uart0: Uart<'a>,
136    pub uart1: Uart<'a>,
137    pub usb: usb::UsbCtrl<'a>,
138    pub watchdog: Watchdog<'a>,
139    pub xosc: Xosc,
140    pub rtc: rtc::Rtc<'a>,
141}
142
143impl Rp2040DefaultPeripherals<'_> {
144    pub fn new() -> Self {
145        Self {
146            adc: adc::Adc::new(),
147            clocks: Clocks::new(),
148            i2c0: i2c::I2c::new_i2c0(),
149            pins: RPPins::new(),
150            pio0: Pio::new_pio0(),
151            pio1: Pio::new_pio1(),
152            pwm: pwm::Pwm::new(),
153            resets: Resets::new(),
154            sio: SIO::new(),
155            spi0: spi::Spi::new_spi0(),
156            sysinfo: sysinfo::SysInfo::new(),
157            timer: RPTimer::new(),
158            uart0: Uart::new_uart0(),
159            uart1: Uart::new_uart1(),
160            usb: usb::UsbCtrl::new(),
161            watchdog: Watchdog::new(),
162            xosc: Xosc::new(),
163            rtc: rtc::Rtc::new(),
164        }
165    }
166
167    pub fn resolve_dependencies(&'static self) {
168        self.pwm.set_clocks(&self.clocks);
169        self.watchdog.resolve_dependencies(&self.resets);
170        self.spi0.set_clocks(&self.clocks);
171        self.uart0.set_clocks(&self.clocks);
172        kernel::deferred_call::DeferredCallClient::register(&self.uart0);
173        kernel::deferred_call::DeferredCallClient::register(&self.uart1);
174        kernel::deferred_call::DeferredCallClient::register(&self.rtc);
175        self.i2c0.resolve_dependencies(&self.clocks, &self.resets);
176        self.usb.set_gpio(self.pins.get_pin(RPGpio::GPIO15));
177        self.rtc.set_clocks(&self.clocks);
178    }
179}
180
181impl InterruptService for Rp2040DefaultPeripherals<'_> {
182    unsafe fn service_interrupt(&self, interrupt: u32) -> bool {
183        match interrupt {
184            interrupts::PIO0_IRQ_0 => {
185                self.pio0.handle_interrupt();
186                true
187            }
188            interrupts::TIMER_IRQ_0 => {
189                self.timer.handle_interrupt();
190                true
191            }
192            interrupts::SIO_IRQ_PROC0 => {
193                self.sio.handle_proc_interrupt(Processor::Processor0);
194                true
195            }
196            interrupts::SIO_IRQ_PROC1 => {
197                self.sio.handle_proc_interrupt(Processor::Processor1);
198                true
199            }
200            interrupts::SPI0_IRQ => {
201                self.spi0.handle_interrupt();
202                true
203            }
204            interrupts::UART0_IRQ => {
205                self.uart0.handle_interrupt();
206                true
207            }
208            interrupts::ADC_IRQ_FIFO => {
209                self.adc.handle_interrupt();
210                true
211            }
212            interrupts::USBCTRL_IRQ => {
213                self.usb.handle_interrupt();
214                true
215            }
216            interrupts::IO_IRQ_BANK0 => {
217                self.pins.handle_interrupt();
218                true
219            }
220
221            interrupts::I2C0_IRQ => {
222                self.i2c0.handle_interrupt();
223                true
224            }
225            interrupts::PWM_IRQ_WRAP => {
226                // As the PWM HIL doesn't provide any support for interrupts, they are
227                // simply ignored.
228                //
229                // Note that PWM interrupts are raised only during unit tests.
230                true
231            }
232            _ => false,
233        }
234    }
235}
rp2040/chip.rs

rp2040/
chip.rs
