lowrisc/registers/
spi_device_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for spi_device.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/spi_device/data/spi_device.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alerts
15pub const SPI_DEVICE_PARAM_NUM_ALERTS: u32 = 1;
16/// Register width
17pub const SPI_DEVICE_PARAM_REG_WIDTH: u32 = 32;
18
19register_structs! {
20    pub SpiDeviceRegisters {
21        /// Interrupt State Register
22        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
23        /// Interrupt Enable Register
24        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
25        /// Interrupt Test Register
26        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
27        /// Alert Test Register
28        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
29        /// Control register
30        (0x0010 => pub(crate) control: ReadWrite<u32, CONTROL::Register>),
31        /// Configuration Register
32        (0x0014 => pub(crate) cfg: ReadWrite<u32, CFG::Register>),
33        /// RX/ TX FIFO levels.
34        (0x0018 => pub(crate) fifo_level: ReadWrite<u32, FIFO_LEVEL::Register>),
35        /// RX/ TX Async FIFO levels between main clk and spi clock
36        (0x001c => pub(crate) async_fifo_level: ReadWrite<u32, ASYNC_FIFO_LEVEL::Register>),
37        /// SPI Device status register
38        (0x0020 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
39        /// Receiver FIFO (SRAM) pointers
40        (0x0024 => pub(crate) rxf_ptr: ReadWrite<u32, RXF_PTR::Register>),
41        /// Transmitter FIFO (SRAM) pointers
42        (0x0028 => pub(crate) txf_ptr: ReadWrite<u32, TXF_PTR::Register>),
43        /// Receiver FIFO (SRAM) Addresses
44        (0x002c => pub(crate) rxf_addr: ReadWrite<u32, RXF_ADDR::Register>),
45        /// Transmitter FIFO (SRAM) Addresses
46        (0x0030 => pub(crate) txf_addr: ReadWrite<u32, TXF_ADDR::Register>),
47        /// Intercept Passthrough datapath.
48        (0x0034 => pub(crate) intercept_en: ReadWrite<u32, INTERCEPT_EN::Register>),
49        /// Last Read Address
50        (0x0038 => pub(crate) last_read_addr: ReadWrite<u32, LAST_READ_ADDR::Register>),
51        /// SPI Flash Status register.
52        (0x003c => pub(crate) flash_status: ReadWrite<u32, FLASH_STATUS::Register>),
53        /// JEDEC Continuation Code configuration register.
54        (0x0040 => pub(crate) jedec_cc: ReadWrite<u32, JEDEC_CC::Register>),
55        /// JEDEC ID register.
56        (0x0044 => pub(crate) jedec_id: ReadWrite<u32, JEDEC_ID::Register>),
57        /// Read Buffer threshold register.
58        (0x0048 => pub(crate) read_threshold: ReadWrite<u32, READ_THRESHOLD::Register>),
59        /// Mailbox Base address register.
60        (0x004c => pub(crate) mailbox_addr: ReadWrite<u32, MAILBOX_ADDR::Register>),
61        /// Upload module status register.
62        (0x0050 => pub(crate) upload_status: ReadWrite<u32, UPLOAD_STATUS::Register>),
63        /// Upload module status 2 register.
64        (0x0054 => pub(crate) upload_status2: ReadWrite<u32, UPLOAD_STATUS2::Register>),
65        /// Command Fifo Read Port.
66        (0x0058 => pub(crate) upload_cmdfifo: ReadWrite<u32, UPLOAD_CMDFIFO::Register>),
67        /// Address Fifo Read Port.
68        (0x005c => pub(crate) upload_addrfifo: ReadWrite<u32, UPLOAD_ADDRFIFO::Register>),
69        /// Command Filter
70        (0x0060 => pub(crate) cmd_filter: [ReadWrite<u32, CMD_FILTER::Register>; 8]),
71        /// Address Swap Mask register.
72        (0x0080 => pub(crate) addr_swap_mask: ReadWrite<u32, ADDR_SWAP_MASK::Register>),
73        /// The address value for the address swap feature.
74        (0x0084 => pub(crate) addr_swap_data: ReadWrite<u32, ADDR_SWAP_DATA::Register>),
75        /// Write Data Swap in the passthrough mode.
76        (0x0088 => pub(crate) payload_swap_mask: ReadWrite<u32, PAYLOAD_SWAP_MASK::Register>),
77        /// Write Data Swap in the passthrough mode.
78        (0x008c => pub(crate) payload_swap_data: ReadWrite<u32, PAYLOAD_SWAP_DATA::Register>),
79        /// Command Info register.
80        (0x0090 => pub(crate) cmd_info: [ReadWrite<u32, CMD_INFO::Register>; 24]),
81        /// Opcode for EN4B.
82        (0x00f0 => pub(crate) cmd_info_en4b: ReadWrite<u32, CMD_INFO_EN4B::Register>),
83        /// Opcode for EX4B
84        (0x00f4 => pub(crate) cmd_info_ex4b: ReadWrite<u32, CMD_INFO_EX4B::Register>),
85        /// Opcode for Write Enable (WREN)
86        (0x00f8 => pub(crate) cmd_info_wren: ReadWrite<u32, CMD_INFO_WREN::Register>),
87        /// Opcode for Write Disable (WRDI)
88        (0x00fc => pub(crate) cmd_info_wrdi: ReadWrite<u32, CMD_INFO_WRDI::Register>),
89        (0x0100 => _reserved1),
90        /// TPM HWIP Capability register.
91        (0x0800 => pub(crate) tpm_cap: ReadWrite<u32, TPM_CAP::Register>),
92        /// TPM Configuration register.
93        (0x0804 => pub(crate) tpm_cfg: ReadWrite<u32, TPM_CFG::Register>),
94        /// TPM submodule state register.
95        (0x0808 => pub(crate) tpm_status: ReadWrite<u32, TPM_STATUS::Register>),
96        /// TPM_ACCESS_x register.
97        (0x080c => pub(crate) tpm_access: [ReadWrite<u32, TPM_ACCESS::Register>; 2]),
98        /// TPM_STS_x register.
99        (0x0814 => pub(crate) tpm_sts: ReadWrite<u32, TPM_STS::Register>),
100        /// TPM_INTF_CAPABILITY
101        (0x0818 => pub(crate) tpm_intf_capability: ReadWrite<u32, TPM_INTF_CAPABILITY::Register>),
102        /// TPM_INT_ENABLE
103        (0x081c => pub(crate) tpm_int_enable: ReadWrite<u32, TPM_INT_ENABLE::Register>),
104        /// TPM_INT_VECTOR
105        (0x0820 => pub(crate) tpm_int_vector: ReadWrite<u32, TPM_INT_VECTOR::Register>),
106        /// TPM_INT_STATUS
107        (0x0824 => pub(crate) tpm_int_status: ReadWrite<u32, TPM_INT_STATUS::Register>),
108        /// TPM_DID/ TPM_VID register
109        (0x0828 => pub(crate) tpm_did_vid: ReadWrite<u32, TPM_DID_VID::Register>),
110        /// TPM_RID
111        (0x082c => pub(crate) tpm_rid: ReadWrite<u32, TPM_RID::Register>),
112        /// TPM Command and Address buffer
113        (0x0830 => pub(crate) tpm_cmd_addr: ReadWrite<u32, TPM_CMD_ADDR::Register>),
114        /// TPM Read command return data FIFO.
115        (0x0834 => pub(crate) tpm_read_fifo: ReadWrite<u32, TPM_READ_FIFO::Register>),
116        /// TPM Write command received data FIFO.
117        (0x0838 => pub(crate) tpm_write_fifo: ReadWrite<u32, TPM_WRITE_FIFO::Register>),
118        (0x083c => _reserved2),
119        /// Memory area: SPI internal buffer.
120        (0x1000 => pub(crate) buffer: [ReadWrite<u32>; 1024]),
121        (0x2000 => @END),
122    }
123}
124
125register_bitfields![u32,
126    /// Common Interrupt Offsets
127    pub(crate) INTR [
128        GENERIC_RX_FULL OFFSET(0) NUMBITS(1) [],
129        GENERIC_RX_WATERMARK OFFSET(1) NUMBITS(1) [],
130        GENERIC_TX_WATERMARK OFFSET(2) NUMBITS(1) [],
131        GENERIC_RX_ERROR OFFSET(3) NUMBITS(1) [],
132        GENERIC_RX_OVERFLOW OFFSET(4) NUMBITS(1) [],
133        GENERIC_TX_UNDERFLOW OFFSET(5) NUMBITS(1) [],
134        UPLOAD_CMDFIFO_NOT_EMPTY OFFSET(6) NUMBITS(1) [],
135        UPLOAD_PAYLOAD_NOT_EMPTY OFFSET(7) NUMBITS(1) [],
136        UPLOAD_PAYLOAD_OVERFLOW OFFSET(8) NUMBITS(1) [],
137        READBUF_WATERMARK OFFSET(9) NUMBITS(1) [],
138        READBUF_FLIP OFFSET(10) NUMBITS(1) [],
139        TPM_HEADER_NOT_EMPTY OFFSET(11) NUMBITS(1) [],
140    ],
141    pub(crate) ALERT_TEST [
142        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
143    ],
144    pub(crate) CONTROL [
145        ABORT OFFSET(0) NUMBITS(1) [],
146        MODE OFFSET(4) NUMBITS(2) [
147            FWMODE = 0,
148            FLASHMODE = 1,
149            PASSTHROUGH = 2,
150        ],
151        RST_TXFIFO OFFSET(16) NUMBITS(1) [],
152        RST_RXFIFO OFFSET(17) NUMBITS(1) [],
153        SRAM_CLK_EN OFFSET(31) NUMBITS(1) [],
154    ],
155    pub(crate) CFG [
156        CPOL OFFSET(0) NUMBITS(1) [],
157        CPHA OFFSET(1) NUMBITS(1) [],
158        TX_ORDER OFFSET(2) NUMBITS(1) [],
159        RX_ORDER OFFSET(3) NUMBITS(1) [],
160        TIMER_V OFFSET(8) NUMBITS(8) [],
161        ADDR_4B_EN OFFSET(16) NUMBITS(1) [],
162        MAILBOX_EN OFFSET(24) NUMBITS(1) [],
163    ],
164    pub(crate) FIFO_LEVEL [
165        RXLVL OFFSET(0) NUMBITS(16) [],
166        TXLVL OFFSET(16) NUMBITS(16) [],
167    ],
168    pub(crate) ASYNC_FIFO_LEVEL [
169        RXLVL OFFSET(0) NUMBITS(8) [],
170        TXLVL OFFSET(16) NUMBITS(8) [],
171    ],
172    pub(crate) STATUS [
173        RXF_FULL OFFSET(0) NUMBITS(1) [],
174        RXF_EMPTY OFFSET(1) NUMBITS(1) [],
175        TXF_FULL OFFSET(2) NUMBITS(1) [],
176        TXF_EMPTY OFFSET(3) NUMBITS(1) [],
177        ABORT_DONE OFFSET(4) NUMBITS(1) [],
178        CSB OFFSET(5) NUMBITS(1) [],
179        TPM_CSB OFFSET(6) NUMBITS(1) [],
180    ],
181    pub(crate) RXF_PTR [
182        RPTR OFFSET(0) NUMBITS(16) [],
183        WPTR OFFSET(16) NUMBITS(16) [],
184    ],
185    pub(crate) TXF_PTR [
186        RPTR OFFSET(0) NUMBITS(16) [],
187        WPTR OFFSET(16) NUMBITS(16) [],
188    ],
189    pub(crate) RXF_ADDR [
190        BASE OFFSET(0) NUMBITS(16) [],
191        LIMIT OFFSET(16) NUMBITS(16) [],
192    ],
193    pub(crate) TXF_ADDR [
194        BASE OFFSET(0) NUMBITS(16) [],
195        LIMIT OFFSET(16) NUMBITS(16) [],
196    ],
197    pub(crate) INTERCEPT_EN [
198        STATUS OFFSET(0) NUMBITS(1) [],
199        JEDEC OFFSET(1) NUMBITS(1) [],
200        SFDP OFFSET(2) NUMBITS(1) [],
201        MBX OFFSET(3) NUMBITS(1) [],
202    ],
203    pub(crate) LAST_READ_ADDR [
204        ADDR OFFSET(0) NUMBITS(32) [],
205    ],
206    pub(crate) FLASH_STATUS [
207        BUSY OFFSET(0) NUMBITS(1) [],
208        STATUS OFFSET(1) NUMBITS(23) [],
209    ],
210    pub(crate) JEDEC_CC [
211        CC OFFSET(0) NUMBITS(8) [],
212        NUM_CC OFFSET(8) NUMBITS(8) [],
213    ],
214    pub(crate) JEDEC_ID [
215        ID OFFSET(0) NUMBITS(16) [],
216        MF OFFSET(16) NUMBITS(8) [],
217    ],
218    pub(crate) READ_THRESHOLD [
219        THRESHOLD OFFSET(0) NUMBITS(10) [],
220    ],
221    pub(crate) MAILBOX_ADDR [
222        ADDR OFFSET(0) NUMBITS(32) [],
223    ],
224    pub(crate) UPLOAD_STATUS [
225        CMDFIFO_DEPTH OFFSET(0) NUMBITS(5) [],
226        CMDFIFO_NOTEMPTY OFFSET(7) NUMBITS(1) [],
227        ADDRFIFO_DEPTH OFFSET(8) NUMBITS(5) [],
228        ADDRFIFO_NOTEMPTY OFFSET(15) NUMBITS(1) [],
229    ],
230    pub(crate) UPLOAD_STATUS2 [
231        PAYLOAD_DEPTH OFFSET(0) NUMBITS(9) [],
232        PAYLOAD_START_IDX OFFSET(16) NUMBITS(8) [],
233    ],
234    pub(crate) UPLOAD_CMDFIFO [
235        DATA OFFSET(0) NUMBITS(8) [],
236    ],
237    pub(crate) UPLOAD_ADDRFIFO [
238        DATA OFFSET(0) NUMBITS(32) [],
239    ],
240    pub(crate) CMD_FILTER [
241        FILTER_0 OFFSET(0) NUMBITS(1) [],
242        FILTER_1 OFFSET(1) NUMBITS(1) [],
243        FILTER_2 OFFSET(2) NUMBITS(1) [],
244        FILTER_3 OFFSET(3) NUMBITS(1) [],
245        FILTER_4 OFFSET(4) NUMBITS(1) [],
246        FILTER_5 OFFSET(5) NUMBITS(1) [],
247        FILTER_6 OFFSET(6) NUMBITS(1) [],
248        FILTER_7 OFFSET(7) NUMBITS(1) [],
249        FILTER_8 OFFSET(8) NUMBITS(1) [],
250        FILTER_9 OFFSET(9) NUMBITS(1) [],
251        FILTER_10 OFFSET(10) NUMBITS(1) [],
252        FILTER_11 OFFSET(11) NUMBITS(1) [],
253        FILTER_12 OFFSET(12) NUMBITS(1) [],
254        FILTER_13 OFFSET(13) NUMBITS(1) [],
255        FILTER_14 OFFSET(14) NUMBITS(1) [],
256        FILTER_15 OFFSET(15) NUMBITS(1) [],
257        FILTER_16 OFFSET(16) NUMBITS(1) [],
258        FILTER_17 OFFSET(17) NUMBITS(1) [],
259        FILTER_18 OFFSET(18) NUMBITS(1) [],
260        FILTER_19 OFFSET(19) NUMBITS(1) [],
261        FILTER_20 OFFSET(20) NUMBITS(1) [],
262        FILTER_21 OFFSET(21) NUMBITS(1) [],
263        FILTER_22 OFFSET(22) NUMBITS(1) [],
264        FILTER_23 OFFSET(23) NUMBITS(1) [],
265        FILTER_24 OFFSET(24) NUMBITS(1) [],
266        FILTER_25 OFFSET(25) NUMBITS(1) [],
267        FILTER_26 OFFSET(26) NUMBITS(1) [],
268        FILTER_27 OFFSET(27) NUMBITS(1) [],
269        FILTER_28 OFFSET(28) NUMBITS(1) [],
270        FILTER_29 OFFSET(29) NUMBITS(1) [],
271        FILTER_30 OFFSET(30) NUMBITS(1) [],
272        FILTER_31 OFFSET(31) NUMBITS(1) [],
273    ],
274    pub(crate) ADDR_SWAP_MASK [
275        MASK OFFSET(0) NUMBITS(32) [],
276    ],
277    pub(crate) ADDR_SWAP_DATA [
278        DATA OFFSET(0) NUMBITS(32) [],
279    ],
280    pub(crate) PAYLOAD_SWAP_MASK [
281        MASK OFFSET(0) NUMBITS(32) [],
282    ],
283    pub(crate) PAYLOAD_SWAP_DATA [
284        DATA OFFSET(0) NUMBITS(32) [],
285    ],
286    pub(crate) CMD_INFO [
287        OPCODE_0 OFFSET(0) NUMBITS(8) [],
288        ADDR_MODE_0 OFFSET(8) NUMBITS(2) [
289            ADDRDISABLED = 0,
290            ADDRCFG = 1,
291            ADDR3B = 2,
292            ADDR4B = 3,
293        ],
294        ADDR_SWAP_EN_0 OFFSET(10) NUMBITS(1) [],
295        MBYTE_EN_0 OFFSET(11) NUMBITS(1) [],
296        DUMMY_SIZE_0 OFFSET(12) NUMBITS(3) [],
297        DUMMY_EN_0 OFFSET(15) NUMBITS(1) [],
298        PAYLOAD_EN_0 OFFSET(16) NUMBITS(4) [],
299        PAYLOAD_DIR_0 OFFSET(20) NUMBITS(1) [
300            PAYLOADIN = 0,
301            PAYLOADOUT = 1,
302        ],
303        PAYLOAD_SWAP_EN_0 OFFSET(21) NUMBITS(1) [],
304        UPLOAD_0 OFFSET(24) NUMBITS(1) [],
305        BUSY_0 OFFSET(25) NUMBITS(1) [],
306        VALID_0 OFFSET(31) NUMBITS(1) [],
307    ],
308    pub(crate) CMD_INFO_EN4B [
309        OPCODE OFFSET(0) NUMBITS(8) [],
310        VALID OFFSET(31) NUMBITS(1) [],
311    ],
312    pub(crate) CMD_INFO_EX4B [
313        OPCODE OFFSET(0) NUMBITS(8) [],
314        VALID OFFSET(31) NUMBITS(1) [],
315    ],
316    pub(crate) CMD_INFO_WREN [
317        OPCODE OFFSET(0) NUMBITS(8) [],
318        VALID OFFSET(31) NUMBITS(1) [],
319    ],
320    pub(crate) CMD_INFO_WRDI [
321        OPCODE OFFSET(0) NUMBITS(8) [],
322        VALID OFFSET(31) NUMBITS(1) [],
323    ],
324    pub(crate) TPM_CAP [
325        REV OFFSET(0) NUMBITS(8) [],
326        LOCALITY OFFSET(8) NUMBITS(1) [],
327        MAX_WR_SIZE OFFSET(16) NUMBITS(3) [],
328        MAX_RD_SIZE OFFSET(20) NUMBITS(3) [],
329    ],
330    pub(crate) TPM_CFG [
331        EN OFFSET(0) NUMBITS(1) [],
332        TPM_MODE OFFSET(1) NUMBITS(1) [],
333        HW_REG_DIS OFFSET(2) NUMBITS(1) [],
334        TPM_REG_CHK_DIS OFFSET(3) NUMBITS(1) [],
335        INVALID_LOCALITY OFFSET(4) NUMBITS(1) [],
336    ],
337    pub(crate) TPM_STATUS [
338        CMDADDR_NOTEMPTY OFFSET(0) NUMBITS(1) [],
339        WRFIFO_DEPTH OFFSET(16) NUMBITS(7) [],
340    ],
341    pub(crate) TPM_ACCESS [
342        ACCESS_0 OFFSET(0) NUMBITS(8) [],
343        ACCESS_1 OFFSET(8) NUMBITS(8) [],
344        ACCESS_2 OFFSET(16) NUMBITS(8) [],
345        ACCESS_3 OFFSET(24) NUMBITS(8) [],
346    ],
347    pub(crate) TPM_STS [
348        STS OFFSET(0) NUMBITS(32) [],
349    ],
350    pub(crate) TPM_INTF_CAPABILITY [
351        INTF_CAPABILITY OFFSET(0) NUMBITS(32) [],
352    ],
353    pub(crate) TPM_INT_ENABLE [
354        INT_ENABLE OFFSET(0) NUMBITS(32) [],
355    ],
356    pub(crate) TPM_INT_VECTOR [
357        INT_VECTOR OFFSET(0) NUMBITS(8) [],
358    ],
359    pub(crate) TPM_INT_STATUS [
360        INT_STATUS OFFSET(0) NUMBITS(32) [],
361    ],
362    pub(crate) TPM_DID_VID [
363        VID OFFSET(0) NUMBITS(16) [],
364        DID OFFSET(16) NUMBITS(16) [],
365    ],
366    pub(crate) TPM_RID [
367        RID OFFSET(0) NUMBITS(8) [],
368    ],
369    pub(crate) TPM_CMD_ADDR [
370        ADDR OFFSET(0) NUMBITS(24) [],
371        CMD OFFSET(24) NUMBITS(8) [],
372    ],
373    pub(crate) TPM_READ_FIFO [
374        VALUE OFFSET(0) NUMBITS(32) [],
375    ],
376    pub(crate) TPM_WRITE_FIFO [
377        VALUE OFFSET(0) NUMBITS(8) [],
378    ],
379];
380
381// End generated register constants for spi_device
lowrisc/registers/spi_device_regs.rs

lowrisc/registers/
spi_device_regs.rs
