lowrisc/registers/
pattgen_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for pattgen.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/pattgen/data/pattgen.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of data registers per each channel
15pub const PATTGEN_PARAM_NUM_REGS_DATA: u32 = 2;
16/// Number of alerts
17pub const PATTGEN_PARAM_NUM_ALERTS: u32 = 1;
18/// Register width
19pub const PATTGEN_PARAM_REG_WIDTH: u32 = 32;
20
21register_structs! {
22    pub PattgenRegisters {
23        /// Interrupt State Register
24        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
25        /// Interrupt Enable Register
26        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
27        /// Interrupt Test Register
28        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
29        /// Alert Test Register
30        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
31        /// PATTGEN control register
32        (0x0010 => pub(crate) ctrl: ReadWrite<u32, CTRL::Register>),
33        /// PATTGEN pre-divider register for Channel 0
34        (0x0014 => pub(crate) prediv_ch0: ReadWrite<u32, PREDIV_CH0::Register>),
35        /// PATTGEN pre-divider register for Channel 1
36        (0x0018 => pub(crate) prediv_ch1: ReadWrite<u32, PREDIV_CH1::Register>),
37        /// PATTGEN seed pattern multi-registers for Channel 0.
38        (0x001c => pub(crate) data_ch0: [ReadWrite<u32, DATA_CH0::Register>; 2]),
39        /// PATTGEN seed pattern multi-registers for Channel 1.
40        (0x0024 => pub(crate) data_ch1: [ReadWrite<u32, DATA_CH1::Register>; 2]),
41        /// PATTGEN pattern length
42        (0x002c => pub(crate) size: ReadWrite<u32, SIZE::Register>),
43        (0x0030 => @END),
44    }
45}
46
47register_bitfields![u32,
48    /// Common Interrupt Offsets
49    pub(crate) INTR [
50        DONE_CH0 OFFSET(0) NUMBITS(1) [],
51        DONE_CH1 OFFSET(1) NUMBITS(1) [],
52    ],
53    pub(crate) ALERT_TEST [
54        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
55    ],
56    pub(crate) CTRL [
57        ENABLE_CH0 OFFSET(0) NUMBITS(1) [],
58        ENABLE_CH1 OFFSET(1) NUMBITS(1) [],
59        POLARITY_CH0 OFFSET(2) NUMBITS(1) [],
60        POLARITY_CH1 OFFSET(3) NUMBITS(1) [],
61    ],
62    pub(crate) PREDIV_CH0 [
63        CLK_RATIO OFFSET(0) NUMBITS(32) [],
64    ],
65    pub(crate) PREDIV_CH1 [
66        CLK_RATIO OFFSET(0) NUMBITS(32) [],
67    ],
68    pub(crate) DATA_CH0 [
69        DATA_0 OFFSET(0) NUMBITS(32) [],
70    ],
71    pub(crate) DATA_CH1 [
72        DATA_0 OFFSET(0) NUMBITS(32) [],
73    ],
74    pub(crate) SIZE [
75        LEN_CH0 OFFSET(0) NUMBITS(6) [],
76        REPS_CH0 OFFSET(6) NUMBITS(10) [],
77        LEN_CH1 OFFSET(16) NUMBITS(6) [],
78        REPS_CH1 OFFSET(22) NUMBITS(10) [],
79    ],
80];
81
82// End generated register constants for pattgen
lowrisc/registers/pattgen_regs.rs

lowrisc/registers/
pattgen_regs.rs
