lowrisc/registers/
otbn_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for otbn.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/otbn/data/otbn.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alerts
15pub const OTBN_PARAM_NUM_ALERTS: u32 = 2;
16/// Register width
17pub const OTBN_PARAM_REG_WIDTH: u32 = 32;
18
19register_structs! {
20    pub OtbnRegisters {
21        /// Interrupt State Register
22        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
23        /// Interrupt Enable Register
24        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
25        /// Interrupt Test Register
26        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
27        /// Alert Test Register
28        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
29        /// Command Register
30        (0x0010 => pub(crate) cmd: ReadWrite<u32, CMD::Register>),
31        /// Control Register
32        (0x0014 => pub(crate) ctrl: ReadWrite<u32, CTRL::Register>),
33        /// Status Register
34        (0x0018 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
35        /// Operation Result Register
36        (0x001c => pub(crate) err_bits: ReadWrite<u32, ERR_BITS::Register>),
37        /// Fatal Alert Cause Register
38        (0x0020 => pub(crate) fatal_alert_cause: ReadWrite<u32, FATAL_ALERT_CAUSE::Register>),
39        /// Instruction Count Register
40        (0x0024 => pub(crate) insn_cnt: ReadWrite<u32, INSN_CNT::Register>),
41        /// A 32-bit CRC checksum of data written to memory
42        (0x0028 => pub(crate) load_checksum: ReadWrite<u32, LOAD_CHECKSUM::Register>),
43        (0x002c => _reserved1),
44        /// Memory area: Instruction Memory Access
45        (0x4000 => pub(crate) imem: [ReadWrite<u32>; 1024]),
46        (0x5000 => _reserved2),
47        /// Memory area: Data Memory Access
48        (0x8000 => pub(crate) dmem: [ReadWrite<u32>; 768]),
49        (0x8c00 => @END),
50    }
51}
52
53register_bitfields![u32,
54    /// Common Interrupt Offsets
55    pub(crate) INTR [
56        DONE OFFSET(0) NUMBITS(1) [],
57    ],
58    pub(crate) ALERT_TEST [
59        FATAL OFFSET(0) NUMBITS(1) [],
60        RECOV OFFSET(1) NUMBITS(1) [],
61    ],
62    pub(crate) CMD [
63        CMD OFFSET(0) NUMBITS(8) [],
64    ],
65    pub(crate) CTRL [
66        SOFTWARE_ERRS_FATAL OFFSET(0) NUMBITS(1) [],
67    ],
68    pub(crate) STATUS [
69        STATUS OFFSET(0) NUMBITS(8) [],
70    ],
71    pub(crate) ERR_BITS [
72        BAD_DATA_ADDR OFFSET(0) NUMBITS(1) [],
73        BAD_INSN_ADDR OFFSET(1) NUMBITS(1) [],
74        CALL_STACK OFFSET(2) NUMBITS(1) [],
75        ILLEGAL_INSN OFFSET(3) NUMBITS(1) [],
76        LOOP OFFSET(4) NUMBITS(1) [],
77        KEY_INVALID OFFSET(5) NUMBITS(1) [],
78        RND_REP_CHK_FAIL OFFSET(6) NUMBITS(1) [],
79        RND_FIPS_CHK_FAIL OFFSET(7) NUMBITS(1) [],
80        IMEM_INTG_VIOLATION OFFSET(16) NUMBITS(1) [],
81        DMEM_INTG_VIOLATION OFFSET(17) NUMBITS(1) [],
82        REG_INTG_VIOLATION OFFSET(18) NUMBITS(1) [],
83        BUS_INTG_VIOLATION OFFSET(19) NUMBITS(1) [],
84        BAD_INTERNAL_STATE OFFSET(20) NUMBITS(1) [],
85        ILLEGAL_BUS_ACCESS OFFSET(21) NUMBITS(1) [],
86        LIFECYCLE_ESCALATION OFFSET(22) NUMBITS(1) [],
87        FATAL_SOFTWARE OFFSET(23) NUMBITS(1) [],
88    ],
89    pub(crate) FATAL_ALERT_CAUSE [
90        IMEM_INTG_VIOLATION OFFSET(0) NUMBITS(1) [],
91        DMEM_INTG_VIOLATION OFFSET(1) NUMBITS(1) [],
92        REG_INTG_VIOLATION OFFSET(2) NUMBITS(1) [],
93        BUS_INTG_VIOLATION OFFSET(3) NUMBITS(1) [],
94        BAD_INTERNAL_STATE OFFSET(4) NUMBITS(1) [],
95        ILLEGAL_BUS_ACCESS OFFSET(5) NUMBITS(1) [],
96        LIFECYCLE_ESCALATION OFFSET(6) NUMBITS(1) [],
97        FATAL_SOFTWARE OFFSET(7) NUMBITS(1) [],
98    ],
99    pub(crate) INSN_CNT [
100        INSN_CNT OFFSET(0) NUMBITS(32) [],
101    ],
102    pub(crate) LOAD_CHECKSUM [
103        CHECKSUM OFFSET(0) NUMBITS(32) [],
104    ],
105];
106
107// End generated register constants for otbn
lowrisc/registers/otbn_regs.rs

lowrisc/registers/
otbn_regs.rs
