lowrisc/registers/
lc_ctrl_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for lc_ctrl.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/lc_ctrl/data/lc_ctrl.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Width of SiliconCreatorId revision field.
15pub const LC_CTRL_PARAM_SILICON_CREATOR_ID_WIDTH: u32 = 16;
16/// Width of ProductId revision field.
17pub const LC_CTRL_PARAM_PRODUCT_ID_WIDTH: u32 = 16;
18/// Width of RevisionId revision field.
19pub const LC_CTRL_PARAM_REVISION_ID_WIDTH: u32 = 8;
20/// Number of 32bit words in a token.
21pub const LC_CTRL_PARAM_NUM_TOKEN_WORDS: u32 = 4;
22/// Number of life cycle state enum bits.
23pub const LC_CTRL_PARAM_CSR_LC_STATE_WIDTH: u32 = 30;
24/// Number of life cycle transition counter bits.
25pub const LC_CTRL_PARAM_CSR_LC_COUNT_WIDTH: u32 = 5;
26/// Number of life cycle id state enum bits.
27pub const LC_CTRL_PARAM_CSR_LC_ID_STATE_WIDTH: u32 = 32;
28/// Number of vendor/test-specific OTP control bits.
29pub const LC_CTRL_PARAM_CSR_OTP_TEST_CTRL_WIDTH: u32 = 32;
30/// Number of vendor/test-specific OTP status bits.
31pub const LC_CTRL_PARAM_CSR_OTP_TEST_STATUS_WIDTH: u32 = 32;
32/// Number of 32bit words in the Device ID.
33pub const LC_CTRL_PARAM_NUM_DEVICE_ID_WORDS: u32 = 8;
34/// Number of 32bit words in the manufacturing state.
35pub const LC_CTRL_PARAM_NUM_MANUF_STATE_WORDS: u32 = 8;
36/// Number of alerts
37pub const LC_CTRL_PARAM_NUM_ALERTS: u32 = 3;
38/// Register width
39pub const LC_CTRL_PARAM_REG_WIDTH: u32 = 32;
40
41register_structs! {
42    pub LcCtrlRegisters {
43        /// Alert Test Register
44        (0x0000 => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
45        /// life cycle status register. Note that all errors are terminal and require a reset cycle.
46        (0x0004 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
47        /// Register write enable for the hardware mutex register.
48        (0x0008 => pub(crate) claim_transition_if_regwen: ReadWrite<u32, CLAIM_TRANSITION_IF_REGWEN::Register>),
49        /// Hardware mutex to claim exclusive access to the transition interface.
50        (0x000c => pub(crate) claim_transition_if: ReadWrite<u32, CLAIM_TRANSITION_IF::Register>),
51        /// Register write enable for all transition interface registers.
52        (0x0010 => pub(crate) transition_regwen: ReadWrite<u32, TRANSITION_REGWEN::Register>),
53        /// Command register for state transition requests.
54        (0x0014 => pub(crate) transition_cmd: ReadWrite<u32, TRANSITION_CMD::Register>),
55        /// Control register for state transition requests.
56        (0x0018 => pub(crate) transition_ctrl: ReadWrite<u32, TRANSITION_CTRL::Register>),
57        /// 128bit token for conditional transitions.
58        (0x001c => pub(crate) transition_token: [ReadWrite<u32, TRANSITION_TOKEN::Register>; 4]),
59        /// This register exposes the decoded life cycle state.
60        (0x002c => pub(crate) transition_target: ReadWrite<u32, TRANSITION_TARGET::Register>),
61        /// Test/vendor-specific settings for the OTP macro wrapper.
62        (0x0030 => pub(crate) otp_vendor_test_ctrl: ReadWrite<u32, OTP_VENDOR_TEST_CTRL::Register>),
63        /// Test/vendor-specific settings for the OTP macro wrapper.
64        (0x0034 => pub(crate) otp_vendor_test_status: ReadWrite<u32, OTP_VENDOR_TEST_STATUS::Register>),
65        /// This register exposes the decoded life cycle state.
66        (0x0038 => pub(crate) lc_state: ReadWrite<u32, LC_STATE::Register>),
67        /// This register exposes the state of the decoded life cycle transition counter.
68        (0x003c => pub(crate) lc_transition_cnt: ReadWrite<u32, LC_TRANSITION_CNT::Register>),
69        /// This register exposes the id state of the device.
70        (0x0040 => pub(crate) lc_id_state: ReadWrite<u32, LC_ID_STATE::Register>),
71        /// This register holds the SILICON_CREATOR_ID and the PRODUCT_ID.
72        (0x0044 => pub(crate) hw_revision0: ReadWrite<u32, HW_REVISION0::Register>),
73        /// This register holds the REVISION_ID.
74        (0x0048 => pub(crate) hw_revision1: ReadWrite<u32, HW_REVISION1::Register>),
75        /// This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP.
76        (0x004c => pub(crate) device_id: [ReadWrite<u32, DEVICE_ID::Register>; 8]),
77        /// This is a 256bit field used for keeping track of the manufacturing state.
78        (0x006c => pub(crate) manuf_state: [ReadWrite<u32, MANUF_STATE::Register>; 8]),
79        (0x008c => @END),
80    }
81}
82
83register_bitfields![u32,
84    pub(crate) ALERT_TEST [
85        FATAL_PROG_ERROR OFFSET(0) NUMBITS(1) [],
86        FATAL_STATE_ERROR OFFSET(1) NUMBITS(1) [],
87        FATAL_BUS_INTEG_ERROR OFFSET(2) NUMBITS(1) [],
88    ],
89    pub(crate) STATUS [
90        INITIALIZED OFFSET(0) NUMBITS(1) [],
91        READY OFFSET(1) NUMBITS(1) [],
92        EXT_CLOCK_SWITCHED OFFSET(2) NUMBITS(1) [],
93        TRANSITION_SUCCESSFUL OFFSET(3) NUMBITS(1) [],
94        TRANSITION_COUNT_ERROR OFFSET(4) NUMBITS(1) [],
95        TRANSITION_ERROR OFFSET(5) NUMBITS(1) [],
96        TOKEN_ERROR OFFSET(6) NUMBITS(1) [],
97        FLASH_RMA_ERROR OFFSET(7) NUMBITS(1) [],
98        OTP_ERROR OFFSET(8) NUMBITS(1) [],
99        STATE_ERROR OFFSET(9) NUMBITS(1) [],
100        BUS_INTEG_ERROR OFFSET(10) NUMBITS(1) [],
101        OTP_PARTITION_ERROR OFFSET(11) NUMBITS(1) [],
102    ],
103    pub(crate) CLAIM_TRANSITION_IF_REGWEN [
104        CLAIM_TRANSITION_IF_REGWEN OFFSET(0) NUMBITS(1) [],
105    ],
106    pub(crate) CLAIM_TRANSITION_IF [
107        MUTEX OFFSET(0) NUMBITS(8) [],
108    ],
109    pub(crate) TRANSITION_REGWEN [
110        TRANSITION_REGWEN OFFSET(0) NUMBITS(1) [],
111    ],
112    pub(crate) TRANSITION_CMD [
113        START OFFSET(0) NUMBITS(1) [],
114    ],
115    pub(crate) TRANSITION_CTRL [
116        EXT_CLOCK_EN OFFSET(0) NUMBITS(1) [],
117        VOLATILE_RAW_UNLOCK OFFSET(1) NUMBITS(1) [],
118    ],
119    pub(crate) TRANSITION_TOKEN [
120        TRANSITION_TOKEN_0 OFFSET(0) NUMBITS(32) [],
121    ],
122    pub(crate) TRANSITION_TARGET [
123        STATE OFFSET(0) NUMBITS(30) [
124            RAW = 0,
125            TEST_UNLOCKED0 = 34636833,
126            TEST_LOCKED0 = 69273666,
127            TEST_UNLOCKED1 = 103910499,
128            TEST_LOCKED1 = 138547332,
129            TEST_UNLOCKED2 = 173184165,
130            TEST_LOCKED2 = 207820998,
131            TEST_UNLOCKED3 = 242457831,
132            TEST_LOCKED3 = 277094664,
133            TEST_UNLOCKED4 = 311731497,
134            TEST_LOCKED4 = 346368330,
135            TEST_UNLOCKED5 = 381005163,
136            TEST_LOCKED5 = 415641996,
137            TEST_UNLOCKED6 = 450278829,
138            TEST_LOCKED6 = 484915662,
139            TEST_UNLOCKED7 = 519552495,
140            DEV = 554189328,
141            PROD = 588826161,
142            PROD_END = 623462994,
143            RMA = 658099827,
144            SCRAP = 692736660,
145        ],
146    ],
147    pub(crate) OTP_VENDOR_TEST_CTRL [
148        OTP_VENDOR_TEST_CTRL OFFSET(0) NUMBITS(32) [],
149    ],
150    pub(crate) OTP_VENDOR_TEST_STATUS [
151        OTP_VENDOR_TEST_STATUS OFFSET(0) NUMBITS(32) [],
152    ],
153    pub(crate) LC_STATE [
154        STATE OFFSET(0) NUMBITS(30) [
155            RAW = 0,
156            TEST_UNLOCKED0 = 34636833,
157            TEST_LOCKED0 = 69273666,
158            TEST_UNLOCKED1 = 103910499,
159            TEST_LOCKED1 = 138547332,
160            TEST_UNLOCKED2 = 173184165,
161            TEST_LOCKED2 = 207820998,
162            TEST_UNLOCKED3 = 242457831,
163            TEST_LOCKED3 = 277094664,
164            TEST_UNLOCKED4 = 311731497,
165            TEST_LOCKED4 = 346368330,
166            TEST_UNLOCKED5 = 381005163,
167            TEST_LOCKED5 = 415641996,
168            TEST_UNLOCKED6 = 450278829,
169            TEST_LOCKED6 = 484915662,
170            TEST_UNLOCKED7 = 519552495,
171            DEV = 554189328,
172            PROD = 588826161,
173            PROD_END = 623462994,
174            RMA = 658099827,
175            SCRAP = 692736660,
176            POST_TRANSITION = 727373493,
177            ESCALATE = 762010326,
178            INVALID = 796647159,
179        ],
180    ],
181    pub(crate) LC_TRANSITION_CNT [
182        CNT OFFSET(0) NUMBITS(5) [],
183    ],
184    pub(crate) LC_ID_STATE [
185        STATE OFFSET(0) NUMBITS(32) [
186            BLANK = 0,
187            PERSONALIZED = 286331153,
188            INVALID = 572662306,
189        ],
190    ],
191    pub(crate) HW_REVISION0 [
192        PRODUCT_ID OFFSET(0) NUMBITS(16) [],
193        SILICON_CREATOR_ID OFFSET(16) NUMBITS(16) [],
194    ],
195    pub(crate) HW_REVISION1 [
196        REVISION_ID OFFSET(0) NUMBITS(8) [],
197        RESERVED OFFSET(8) NUMBITS(24) [],
198    ],
199    pub(crate) DEVICE_ID [
200        DEVICE_ID_0 OFFSET(0) NUMBITS(32) [],
201    ],
202    pub(crate) MANUF_STATE [
203        MANUF_STATE_0 OFFSET(0) NUMBITS(32) [],
204    ],
205];
206
207// End generated register constants for lc_ctrl
lowrisc/registers/lc_ctrl_regs.rs

lowrisc/registers/
lc_ctrl_regs.rs
