lowrisc/registers/
gpio_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for gpio.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/gpio/data/gpio.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alerts
15pub const GPIO_PARAM_NUM_ALERTS: u32 = 1;
16/// Register width
17pub const GPIO_PARAM_REG_WIDTH: u32 = 32;
18
19register_structs! {
20    pub GpioRegisters {
21        /// Interrupt State Register
22        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
23        /// Interrupt Enable Register
24        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
25        /// Interrupt Test Register
26        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
27        /// Alert Test Register
28        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
29        /// GPIO Input data read value
30        (0x0010 => pub(crate) data_in: ReadWrite<u32, DATA_IN::Register>),
31        /// GPIO direct output data write value
32        (0x0014 => pub(crate) direct_out: ReadWrite<u32, DIRECT_OUT::Register>),
33        /// GPIO write data lower with mask.
34        (0x0018 => pub(crate) masked_out_lower: ReadWrite<u32, MASKED_OUT_LOWER::Register>),
35        /// GPIO write data upper with mask.
36        (0x001c => pub(crate) masked_out_upper: ReadWrite<u32, MASKED_OUT_UPPER::Register>),
37        /// GPIO Output Enable.
38        (0x0020 => pub(crate) direct_oe: ReadWrite<u32, DIRECT_OE::Register>),
39        /// GPIO write Output Enable lower with mask.
40        (0x0024 => pub(crate) masked_oe_lower: ReadWrite<u32, MASKED_OE_LOWER::Register>),
41        /// GPIO write Output Enable upper with mask.
42        (0x0028 => pub(crate) masked_oe_upper: ReadWrite<u32, MASKED_OE_UPPER::Register>),
43        /// GPIO interrupt enable for GPIO, rising edge.
44        (0x002c => pub(crate) intr_ctrl_en_rising: ReadWrite<u32, INTR::Register>),
45        /// GPIO interrupt enable for GPIO, falling edge.
46        (0x0030 => pub(crate) intr_ctrl_en_falling: ReadWrite<u32, INTR::Register>),
47        /// GPIO interrupt enable for GPIO, level high.
48        (0x0034 => pub(crate) intr_ctrl_en_lvlhigh: ReadWrite<u32, INTR::Register>),
49        /// GPIO interrupt enable for GPIO, level low.
50        (0x0038 => pub(crate) intr_ctrl_en_lvllow: ReadWrite<u32, INTR::Register>),
51        /// filter enable for GPIO input bits.
52        (0x003c => pub(crate) ctrl_en_input_filter: ReadWrite<u32, CTRL_EN_INPUT_FILTER::Register>),
53        (0x0040 => @END),
54    }
55}
56
57register_bitfields![u32,
58    /// Common Interrupt Offsets
59    pub(crate) INTR [
60        GPIO_0 OFFSET(0) NUMBITS(1) [],
61        GPIO_1 OFFSET(1) NUMBITS(1) [],
62        GPIO_2 OFFSET(2) NUMBITS(1) [],
63        GPIO_3 OFFSET(3) NUMBITS(1) [],
64        GPIO_4 OFFSET(4) NUMBITS(1) [],
65        GPIO_5 OFFSET(5) NUMBITS(1) [],
66        GPIO_6 OFFSET(6) NUMBITS(1) [],
67        GPIO_7 OFFSET(7) NUMBITS(1) [],
68        GPIO_8 OFFSET(8) NUMBITS(1) [],
69        GPIO_9 OFFSET(9) NUMBITS(1) [],
70        GPIO_10 OFFSET(10) NUMBITS(1) [],
71        GPIO_11 OFFSET(11) NUMBITS(1) [],
72        GPIO_12 OFFSET(12) NUMBITS(1) [],
73        GPIO_13 OFFSET(13) NUMBITS(1) [],
74        GPIO_14 OFFSET(14) NUMBITS(1) [],
75        GPIO_15 OFFSET(15) NUMBITS(1) [],
76        GPIO_16 OFFSET(16) NUMBITS(1) [],
77        GPIO_17 OFFSET(17) NUMBITS(1) [],
78        GPIO_18 OFFSET(18) NUMBITS(1) [],
79        GPIO_19 OFFSET(19) NUMBITS(1) [],
80        GPIO_20 OFFSET(20) NUMBITS(1) [],
81        GPIO_21 OFFSET(21) NUMBITS(1) [],
82        GPIO_22 OFFSET(22) NUMBITS(1) [],
83        GPIO_23 OFFSET(23) NUMBITS(1) [],
84        GPIO_24 OFFSET(24) NUMBITS(1) [],
85        GPIO_25 OFFSET(25) NUMBITS(1) [],
86        GPIO_26 OFFSET(26) NUMBITS(1) [],
87        GPIO_27 OFFSET(27) NUMBITS(1) [],
88        GPIO_28 OFFSET(28) NUMBITS(1) [],
89        GPIO_29 OFFSET(29) NUMBITS(1) [],
90        GPIO_30 OFFSET(30) NUMBITS(1) [],
91        GPIO_31 OFFSET(31) NUMBITS(1) [],
92    ],
93    pub(crate) ALERT_TEST [
94        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
95    ],
96    pub(crate) DATA_IN [
97        DATA_IN OFFSET(0) NUMBITS(32) [],
98    ],
99    pub(crate) DIRECT_OUT [
100        DIRECT_OUT OFFSET(0) NUMBITS(32) [],
101    ],
102    pub(crate) MASKED_OUT_LOWER [
103        DATA OFFSET(0) NUMBITS(16) [],
104        MASK OFFSET(16) NUMBITS(16) [],
105    ],
106    pub(crate) MASKED_OUT_UPPER [
107        DATA OFFSET(0) NUMBITS(16) [],
108        MASK OFFSET(16) NUMBITS(16) [],
109    ],
110    pub(crate) DIRECT_OE [
111        DIRECT_OE_0 OFFSET(0) NUMBITS(1) [],
112        DIRECT_OE_1 OFFSET(1) NUMBITS(1) [],
113        DIRECT_OE_2 OFFSET(2) NUMBITS(1) [],
114        DIRECT_OE_3 OFFSET(3) NUMBITS(1) [],
115        DIRECT_OE_4 OFFSET(4) NUMBITS(1) [],
116        DIRECT_OE_5 OFFSET(5) NUMBITS(1) [],
117        DIRECT_OE_6 OFFSET(6) NUMBITS(1) [],
118        DIRECT_OE_7 OFFSET(7) NUMBITS(1) [],
119        DIRECT_OE_8 OFFSET(8) NUMBITS(1) [],
120        DIRECT_OE_9 OFFSET(9) NUMBITS(1) [],
121        DIRECT_OE_10 OFFSET(10) NUMBITS(1) [],
122        DIRECT_OE_11 OFFSET(11) NUMBITS(1) [],
123        DIRECT_OE_12 OFFSET(12) NUMBITS(1) [],
124        DIRECT_OE_13 OFFSET(13) NUMBITS(1) [],
125        DIRECT_OE_14 OFFSET(14) NUMBITS(1) [],
126        DIRECT_OE_15 OFFSET(15) NUMBITS(1) [],
127        DIRECT_OE_16 OFFSET(16) NUMBITS(1) [],
128        DIRECT_OE_17 OFFSET(17) NUMBITS(1) [],
129        DIRECT_OE_18 OFFSET(18) NUMBITS(1) [],
130        DIRECT_OE_19 OFFSET(19) NUMBITS(1) [],
131        DIRECT_OE_20 OFFSET(20) NUMBITS(1) [],
132        DIRECT_OE_21 OFFSET(21) NUMBITS(1) [],
133        DIRECT_OE_22 OFFSET(22) NUMBITS(1) [],
134        DIRECT_OE_23 OFFSET(23) NUMBITS(1) [],
135        DIRECT_OE_24 OFFSET(24) NUMBITS(1) [],
136        DIRECT_OE_25 OFFSET(25) NUMBITS(1) [],
137        DIRECT_OE_26 OFFSET(26) NUMBITS(1) [],
138        DIRECT_OE_27 OFFSET(27) NUMBITS(1) [],
139        DIRECT_OE_28 OFFSET(28) NUMBITS(1) [],
140        DIRECT_OE_29 OFFSET(29) NUMBITS(1) [],
141        DIRECT_OE_30 OFFSET(30) NUMBITS(1) [],
142        DIRECT_OE_31 OFFSET(31) NUMBITS(1) [],
143    ],
144    pub(crate) MASKED_OE_LOWER [
145        DATA OFFSET(0) NUMBITS(16) [],
146        MASK OFFSET(16) NUMBITS(16) [],
147    ],
148    pub(crate) MASKED_OE_UPPER [
149        DATA OFFSET(0) NUMBITS(16) [],
150        MASK OFFSET(16) NUMBITS(16) [],
151    ],
152    pub(crate) CTRL_EN_INPUT_FILTER [
153        CTRL_EN_INPUT_FILTER OFFSET(0) NUMBITS(32) [],
154    ],
155];
156
157// End generated register constants for gpio
lowrisc/registers/gpio_regs.rs

lowrisc/registers/
gpio_regs.rs
