lowrisc/registers/
flash_ctrl_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for flash_ctrl.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/flash_ctrl/data/flash_ctrl.hjson
12use kernel::utilities::registers::ReadOnly;
13use kernel::utilities::registers::ReadWrite;
14use kernel::utilities::registers::WriteOnly;
15use kernel::utilities::registers::{register_bitfields, register_structs};
16/// Number of flash banks
17pub const FLASH_CTRL_PARAM_REG_NUM_BANKS: u32 = 2;
18/// Number of pages per bank
19pub const FLASH_CTRL_PARAM_REG_PAGES_PER_BANK: u32 = 256;
20/// Program resolution window in bytes
21pub const FLASH_CTRL_PARAM_REG_BUS_PGM_RES_BYTES: u32 = 64;
22/// Number of bits needed to represent the pages within a bank
23pub const FLASH_CTRL_PARAM_REG_PAGE_WIDTH: u32 = 8;
24/// Number of bits needed to represent the number of banks
25pub const FLASH_CTRL_PARAM_REG_BANK_WIDTH: u32 = 1;
26/// Number of configurable flash regions
27pub const FLASH_CTRL_PARAM_NUM_REGIONS: u32 = 8;
28/// Number of info partition types
29pub const FLASH_CTRL_PARAM_NUM_INFO_TYPES: u32 = 3;
30/// Number of configurable flash info pages for info type 0
31pub const FLASH_CTRL_PARAM_NUM_INFOS0: u32 = 10;
32/// Number of configurable flash info pages for info type 1
33pub const FLASH_CTRL_PARAM_NUM_INFOS1: u32 = 1;
34/// Number of configurable flash info pages for info type 2
35pub const FLASH_CTRL_PARAM_NUM_INFOS2: u32 = 2;
36/// Number of words per page
37pub const FLASH_CTRL_PARAM_WORDS_PER_PAGE: u32 = 256;
38/// Number of bytes per word
39pub const FLASH_CTRL_PARAM_BYTES_PER_WORD: u32 = 8;
40/// Number of bytes per page
41pub const FLASH_CTRL_PARAM_BYTES_PER_PAGE: u32 = 2048;
42/// Number of bytes per bank
43pub const FLASH_CTRL_PARAM_BYTES_PER_BANK: u32 = 524288;
44/// Maximum depth for read / program fifos
45pub const FLASH_CTRL_PARAM_MAX_FIFO_DEPTH: u32 = 16;
46/// Maximum depth for read / program fifos
47pub const FLASH_CTRL_PARAM_MAX_FIFO_WIDTH: u32 = 5;
48/// Number of alerts
49pub const FLASH_CTRL_PARAM_NUM_ALERTS: u32 = 5;
50/// Register width
51pub const FLASH_CTRL_PARAM_REG_WIDTH: u32 = 32;
52
53register_structs! {
54    pub FlashCtrlRegisters {
55        /// Interrupt State Register
56        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
57        /// Interrupt Enable Register
58        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
59        /// Interrupt Test Register
60        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
61        /// Alert Test Register
62        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
63        /// Disable flash functionality
64        (0x0010 => pub(crate) dis: ReadWrite<u32, DIS::Register>),
65        /// Controls whether flash can be used for code execution fetches
66        (0x0014 => pub(crate) exec: ReadWrite<u32, EXEC::Register>),
67        /// Controller init register
68        (0x0018 => pub(crate) init: ReadWrite<u32, INIT::Register>),
69        /// Controls the configurability of the !!CONTROL register.
70        (0x001c => pub(crate) ctrl_regwen: ReadWrite<u32, CTRL_REGWEN::Register>),
71        /// Control register
72        (0x0020 => pub(crate) control: ReadWrite<u32, CONTROL::Register>),
73        /// Address for flash operation
74        (0x0024 => pub(crate) addr: ReadWrite<u32, ADDR::Register>),
75        /// Enable different program types
76        (0x0028 => pub(crate) prog_type_en: ReadWrite<u32, PROG_TYPE_EN::Register>),
77        /// Suspend erase
78        (0x002c => pub(crate) erase_suspend: ReadWrite<u32, ERASE_SUSPEND::Register>),
79        /// Memory region registers configuration enable.
80        (0x0030 => pub(crate) region_cfg_regwen: [ReadWrite<u32, REGION_CFG_REGWEN::Register>; 8]),
81        /// Memory property configuration for data partition
82        (0x0050 => pub(crate) mp_region_cfg: [ReadWrite<u32, MP_REGION_CFG::Register>; 8]),
83        /// Memory base and size configuration for data partition
84        (0x0070 => pub(crate) mp_region: [ReadWrite<u32, MP_REGION::Register>; 8]),
85        /// Default region properties
86        (0x0090 => pub(crate) default_region: ReadWrite<u32, DEFAULT_REGION::Register>),
87        /// Memory region registers configuration enable.
88        (0x0094 => pub(crate) bank0_info0_regwen: [ReadWrite<u32, BANK0_INFO0_REGWEN::Register>; 10]),
89        ///   Memory property configuration for info partition in bank0,
90        (0x00bc => pub(crate) bank0_info0_page_cfg: [ReadWrite<u32, BANK0_INFO0_PAGE_CFG::Register>; 10]),
91        /// Memory region registers configuration enable.
92        (0x00e4 => pub(crate) bank0_info1_regwen: [ReadWrite<u32, BANK0_INFO1_REGWEN::Register>; 1]),
93        ///   Memory property configuration for info partition in bank0,
94        (0x00e8 => pub(crate) bank0_info1_page_cfg: [ReadWrite<u32, BANK0_INFO1_PAGE_CFG::Register>; 1]),
95        /// Memory region registers configuration enable.
96        (0x00ec => pub(crate) bank0_info2_regwen: [ReadWrite<u32, BANK0_INFO2_REGWEN::Register>; 2]),
97        ///   Memory property configuration for info partition in bank0,
98        (0x00f4 => pub(crate) bank0_info2_page_cfg: [ReadWrite<u32, BANK0_INFO2_PAGE_CFG::Register>; 2]),
99        /// Memory region registers configuration enable.
100        (0x00fc => pub(crate) bank1_info0_regwen: [ReadWrite<u32, BANK1_INFO0_REGWEN::Register>; 10]),
101        ///   Memory property configuration for info partition in bank1,
102        (0x0124 => pub(crate) bank1_info0_page_cfg: [ReadWrite<u32, BANK1_INFO0_PAGE_CFG::Register>; 10]),
103        /// Memory region registers configuration enable.
104        (0x014c => pub(crate) bank1_info1_regwen: [ReadWrite<u32, BANK1_INFO1_REGWEN::Register>; 1]),
105        ///   Memory property configuration for info partition in bank1,
106        (0x0150 => pub(crate) bank1_info1_page_cfg: [ReadWrite<u32, BANK1_INFO1_PAGE_CFG::Register>; 1]),
107        /// Memory region registers configuration enable.
108        (0x0154 => pub(crate) bank1_info2_regwen: [ReadWrite<u32, BANK1_INFO2_REGWEN::Register>; 2]),
109        ///   Memory property configuration for info partition in bank1,
110        (0x015c => pub(crate) bank1_info2_page_cfg: [ReadWrite<u32, BANK1_INFO2_PAGE_CFG::Register>; 2]),
111        /// HW interface info configuration rule overrides
112        (0x0164 => pub(crate) hw_info_cfg_override: ReadWrite<u32, HW_INFO_CFG_OVERRIDE::Register>),
113        /// Bank configuration registers configuration enable.
114        (0x0168 => pub(crate) bank_cfg_regwen: ReadWrite<u32, BANK_CFG_REGWEN::Register>),
115        /// Memory properties bank configuration
116        (0x016c => pub(crate) mp_bank_cfg_shadowed: [ReadWrite<u32, MP_BANK_CFG_SHADOWED::Register>; 1]),
117        /// Flash Operation Status
118        (0x0170 => pub(crate) op_status: ReadWrite<u32, OP_STATUS::Register>),
119        /// Flash Controller Status
120        (0x0174 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
121        /// Current flash fsm state
122        (0x0178 => pub(crate) debug_state: ReadWrite<u32, DEBUG_STATE::Register>),
123        /// Flash error code register.
124        (0x017c => pub(crate) err_code: ReadWrite<u32, ERR_CODE::Register>),
125        /// This register tabulates standard fault status of the flash.
126        (0x0180 => pub(crate) std_fault_status: ReadWrite<u32, STD_FAULT_STATUS::Register>),
127        /// This register tabulates customized fault status of the flash.
128        (0x0184 => pub(crate) fault_status: ReadWrite<u32, FAULT_STATUS::Register>),
129        /// Synchronous error address
130        (0x0188 => pub(crate) err_addr: ReadWrite<u32, ERR_ADDR::Register>),
131        /// Total number of single bit ECC error count
132        (0x018c => pub(crate) ecc_single_err_cnt: [ReadWrite<u32, ECC_SINGLE_ERR_CNT::Register>; 1]),
133        /// Latest address of ECC single err
134        (0x0190 => pub(crate) ecc_single_err_addr: [ReadWrite<u32, ECC_SINGLE_ERR_ADDR::Register>; 2]),
135        /// Phy alert configuration
136        (0x0198 => pub(crate) phy_alert_cfg: ReadWrite<u32, PHY_ALERT_CFG::Register>),
137        /// Flash Phy Status
138        (0x019c => pub(crate) phy_status: ReadWrite<u32, PHY_STATUS::Register>),
139        /// Flash Controller Scratch
140        (0x01a0 => pub(crate) scratch: ReadWrite<u32, SCRATCH::Register>),
141        /// Programmable depth where FIFOs should generate interrupts
142        (0x01a4 => pub(crate) fifo_lvl: ReadWrite<u32, FIFO_LVL::Register>),
143        /// Reset for flash controller FIFOs
144        (0x01a8 => pub(crate) fifo_rst: ReadWrite<u32, FIFO_RST::Register>),
145        /// Current program and read fifo depth
146        (0x01ac => pub(crate) curr_fifo_lvl: ReadWrite<u32, CURR_FIFO_LVL::Register>),
147        /// Memory area: Flash program FIFO.
148        (0x01b0 => pub(crate) prog_fifo: [WriteOnly<u32>; 1]),
149        /// Memory area: Flash read FIFO.
150        (0x01b4 => pub(crate) rd_fifo: [ReadOnly<u32>; 1]),
151        (0x01b8 => @END),
152    }
153}
154
155register_bitfields![u32,
156    /// Common Interrupt Offsets
157    pub(crate) INTR [
158        PROG_EMPTY OFFSET(0) NUMBITS(1) [],
159        PROG_LVL OFFSET(1) NUMBITS(1) [],
160        RD_FULL OFFSET(2) NUMBITS(1) [],
161        RD_LVL OFFSET(3) NUMBITS(1) [],
162        OP_DONE OFFSET(4) NUMBITS(1) [],
163        CORR_ERR OFFSET(5) NUMBITS(1) [],
164    ],
165    pub(crate) ALERT_TEST [
166        RECOV_ERR OFFSET(0) NUMBITS(1) [],
167        FATAL_STD_ERR OFFSET(1) NUMBITS(1) [],
168        FATAL_ERR OFFSET(2) NUMBITS(1) [],
169        FATAL_PRIM_FLASH_ALERT OFFSET(3) NUMBITS(1) [],
170        RECOV_PRIM_FLASH_ALERT OFFSET(4) NUMBITS(1) [],
171    ],
172    pub(crate) DIS [
173        VAL OFFSET(0) NUMBITS(4) [],
174    ],
175    pub(crate) EXEC [
176        EN OFFSET(0) NUMBITS(32) [],
177    ],
178    pub(crate) INIT [
179        VAL OFFSET(0) NUMBITS(1) [],
180    ],
181    pub(crate) CTRL_REGWEN [
182        EN OFFSET(0) NUMBITS(1) [],
183    ],
184    pub(crate) CONTROL [
185        START OFFSET(0) NUMBITS(1) [],
186        OP OFFSET(4) NUMBITS(2) [
187            READ = 0,
188            PROG = 1,
189            ERASE = 2,
190        ],
191        PROG_SEL OFFSET(6) NUMBITS(1) [
192            NORMAL_PROGRAM = 0,
193            PROGRAM_REPAIR = 1,
194        ],
195        ERASE_SEL OFFSET(7) NUMBITS(1) [
196            PAGE_ERASE = 0,
197            BANK_ERASE = 1,
198        ],
199        PARTITION_SEL OFFSET(8) NUMBITS(1) [],
200        INFO_SEL OFFSET(9) NUMBITS(2) [],
201        NUM OFFSET(16) NUMBITS(12) [],
202    ],
203    pub(crate) ADDR [
204        START OFFSET(0) NUMBITS(20) [],
205    ],
206    pub(crate) PROG_TYPE_EN [
207        NORMAL OFFSET(0) NUMBITS(1) [],
208        REPAIR OFFSET(1) NUMBITS(1) [],
209    ],
210    pub(crate) ERASE_SUSPEND [
211        REQ OFFSET(0) NUMBITS(1) [],
212    ],
213    pub(crate) REGION_CFG_REGWEN [
214        REGION_0 OFFSET(0) NUMBITS(1) [
215            REGION_LOCKED = 0,
216            REGION_ENABLED = 1,
217        ],
218    ],
219    pub(crate) MP_REGION_CFG [
220        EN_0 OFFSET(0) NUMBITS(4) [],
221        RD_EN_0 OFFSET(4) NUMBITS(4) [],
222        PROG_EN_0 OFFSET(8) NUMBITS(4) [],
223        ERASE_EN_0 OFFSET(12) NUMBITS(4) [],
224        SCRAMBLE_EN_0 OFFSET(16) NUMBITS(4) [],
225        ECC_EN_0 OFFSET(20) NUMBITS(4) [],
226        HE_EN_0 OFFSET(24) NUMBITS(4) [],
227    ],
228    pub(crate) MP_REGION [
229        BASE_0 OFFSET(0) NUMBITS(9) [],
230        SIZE_0 OFFSET(9) NUMBITS(10) [],
231    ],
232    pub(crate) DEFAULT_REGION [
233        RD_EN OFFSET(0) NUMBITS(4) [],
234        PROG_EN OFFSET(4) NUMBITS(4) [],
235        ERASE_EN OFFSET(8) NUMBITS(4) [],
236        SCRAMBLE_EN OFFSET(12) NUMBITS(4) [],
237        ECC_EN OFFSET(16) NUMBITS(4) [],
238        HE_EN OFFSET(20) NUMBITS(4) [],
239    ],
240    pub(crate) BANK0_INFO0_REGWEN [
241        REGION_0 OFFSET(0) NUMBITS(1) [
242            PAGE_LOCKED = 0,
243            PAGE_ENABLED = 1,
244        ],
245    ],
246    pub(crate) BANK0_INFO0_PAGE_CFG [
247        EN_0 OFFSET(0) NUMBITS(4) [],
248        RD_EN_0 OFFSET(4) NUMBITS(4) [],
249        PROG_EN_0 OFFSET(8) NUMBITS(4) [],
250        ERASE_EN_0 OFFSET(12) NUMBITS(4) [],
251        SCRAMBLE_EN_0 OFFSET(16) NUMBITS(4) [],
252        ECC_EN_0 OFFSET(20) NUMBITS(4) [],
253        HE_EN_0 OFFSET(24) NUMBITS(4) [],
254    ],
255    pub(crate) BANK0_INFO1_REGWEN [
256        REGION_0 OFFSET(0) NUMBITS(1) [
257            PAGE_LOCKED = 0,
258            PAGE_ENABLED = 1,
259        ],
260    ],
261    pub(crate) BANK0_INFO1_PAGE_CFG [
262        EN_0 OFFSET(0) NUMBITS(4) [],
263        RD_EN_0 OFFSET(4) NUMBITS(4) [],
264        PROG_EN_0 OFFSET(8) NUMBITS(4) [],
265        ERASE_EN_0 OFFSET(12) NUMBITS(4) [],
266        SCRAMBLE_EN_0 OFFSET(16) NUMBITS(4) [],
267        ECC_EN_0 OFFSET(20) NUMBITS(4) [],
268        HE_EN_0 OFFSET(24) NUMBITS(4) [],
269    ],
270    pub(crate) BANK0_INFO2_REGWEN [
271        REGION_0 OFFSET(0) NUMBITS(1) [
272            PAGE_LOCKED = 0,
273            PAGE_ENABLED = 1,
274        ],
275    ],
276    pub(crate) BANK0_INFO2_PAGE_CFG [
277        EN_0 OFFSET(0) NUMBITS(4) [],
278        RD_EN_0 OFFSET(4) NUMBITS(4) [],
279        PROG_EN_0 OFFSET(8) NUMBITS(4) [],
280        ERASE_EN_0 OFFSET(12) NUMBITS(4) [],
281        SCRAMBLE_EN_0 OFFSET(16) NUMBITS(4) [],
282        ECC_EN_0 OFFSET(20) NUMBITS(4) [],
283        HE_EN_0 OFFSET(24) NUMBITS(4) [],
284    ],
285    pub(crate) BANK1_INFO0_REGWEN [
286        REGION_0 OFFSET(0) NUMBITS(1) [
287            PAGE_LOCKED = 0,
288            PAGE_ENABLED = 1,
289        ],
290    ],
291    pub(crate) BANK1_INFO0_PAGE_CFG [
292        EN_0 OFFSET(0) NUMBITS(4) [],
293        RD_EN_0 OFFSET(4) NUMBITS(4) [],
294        PROG_EN_0 OFFSET(8) NUMBITS(4) [],
295        ERASE_EN_0 OFFSET(12) NUMBITS(4) [],
296        SCRAMBLE_EN_0 OFFSET(16) NUMBITS(4) [],
297        ECC_EN_0 OFFSET(20) NUMBITS(4) [],
298        HE_EN_0 OFFSET(24) NUMBITS(4) [],
299    ],
300    pub(crate) BANK1_INFO1_REGWEN [
301        REGION_0 OFFSET(0) NUMBITS(1) [
302            PAGE_LOCKED = 0,
303            PAGE_ENABLED = 1,
304        ],
305    ],
306    pub(crate) BANK1_INFO1_PAGE_CFG [
307        EN_0 OFFSET(0) NUMBITS(4) [],
308        RD_EN_0 OFFSET(4) NUMBITS(4) [],
309        PROG_EN_0 OFFSET(8) NUMBITS(4) [],
310        ERASE_EN_0 OFFSET(12) NUMBITS(4) [],
311        SCRAMBLE_EN_0 OFFSET(16) NUMBITS(4) [],
312        ECC_EN_0 OFFSET(20) NUMBITS(4) [],
313        HE_EN_0 OFFSET(24) NUMBITS(4) [],
314    ],
315    pub(crate) BANK1_INFO2_REGWEN [
316        REGION_0 OFFSET(0) NUMBITS(1) [
317            PAGE_LOCKED = 0,
318            PAGE_ENABLED = 1,
319        ],
320    ],
321    pub(crate) BANK1_INFO2_PAGE_CFG [
322        EN_0 OFFSET(0) NUMBITS(4) [],
323        RD_EN_0 OFFSET(4) NUMBITS(4) [],
324        PROG_EN_0 OFFSET(8) NUMBITS(4) [],
325        ERASE_EN_0 OFFSET(12) NUMBITS(4) [],
326        SCRAMBLE_EN_0 OFFSET(16) NUMBITS(4) [],
327        ECC_EN_0 OFFSET(20) NUMBITS(4) [],
328        HE_EN_0 OFFSET(24) NUMBITS(4) [],
329    ],
330    pub(crate) HW_INFO_CFG_OVERRIDE [
331        SCRAMBLE_DIS OFFSET(0) NUMBITS(4) [],
332        ECC_DIS OFFSET(4) NUMBITS(4) [],
333    ],
334    pub(crate) BANK_CFG_REGWEN [
335        BANK OFFSET(0) NUMBITS(1) [
336            BANK_LOCKED = 0,
337            BANK_ENABLED = 1,
338        ],
339    ],
340    pub(crate) MP_BANK_CFG_SHADOWED [
341        ERASE_EN_0 OFFSET(0) NUMBITS(1) [],
342        ERASE_EN_1 OFFSET(1) NUMBITS(1) [],
343    ],
344    pub(crate) OP_STATUS [
345        DONE OFFSET(0) NUMBITS(1) [],
346        ERR OFFSET(1) NUMBITS(1) [],
347    ],
348    pub(crate) STATUS [
349        RD_FULL OFFSET(0) NUMBITS(1) [],
350        RD_EMPTY OFFSET(1) NUMBITS(1) [],
351        PROG_FULL OFFSET(2) NUMBITS(1) [],
352        PROG_EMPTY OFFSET(3) NUMBITS(1) [],
353        INIT_WIP OFFSET(4) NUMBITS(1) [],
354        INITIALIZED OFFSET(5) NUMBITS(1) [],
355    ],
356    pub(crate) DEBUG_STATE [
357        LCMGR_STATE OFFSET(0) NUMBITS(11) [],
358    ],
359    pub(crate) ERR_CODE [
360        OP_ERR OFFSET(0) NUMBITS(1) [],
361        MP_ERR OFFSET(1) NUMBITS(1) [],
362        RD_ERR OFFSET(2) NUMBITS(1) [],
363        PROG_ERR OFFSET(3) NUMBITS(1) [],
364        PROG_WIN_ERR OFFSET(4) NUMBITS(1) [],
365        PROG_TYPE_ERR OFFSET(5) NUMBITS(1) [],
366        UPDATE_ERR OFFSET(6) NUMBITS(1) [],
367        MACRO_ERR OFFSET(7) NUMBITS(1) [],
368    ],
369    pub(crate) STD_FAULT_STATUS [
370        REG_INTG_ERR OFFSET(0) NUMBITS(1) [],
371        PROG_INTG_ERR OFFSET(1) NUMBITS(1) [],
372        LCMGR_ERR OFFSET(2) NUMBITS(1) [],
373        LCMGR_INTG_ERR OFFSET(3) NUMBITS(1) [],
374        ARB_FSM_ERR OFFSET(4) NUMBITS(1) [],
375        STORAGE_ERR OFFSET(5) NUMBITS(1) [],
376        PHY_FSM_ERR OFFSET(6) NUMBITS(1) [],
377        CTRL_CNT_ERR OFFSET(7) NUMBITS(1) [],
378        FIFO_ERR OFFSET(8) NUMBITS(1) [],
379    ],
380    pub(crate) FAULT_STATUS [
381        OP_ERR OFFSET(0) NUMBITS(1) [],
382        MP_ERR OFFSET(1) NUMBITS(1) [],
383        RD_ERR OFFSET(2) NUMBITS(1) [],
384        PROG_ERR OFFSET(3) NUMBITS(1) [],
385        PROG_WIN_ERR OFFSET(4) NUMBITS(1) [],
386        PROG_TYPE_ERR OFFSET(5) NUMBITS(1) [],
387        SEED_ERR OFFSET(6) NUMBITS(1) [],
388        PHY_RELBL_ERR OFFSET(7) NUMBITS(1) [],
389        PHY_STORAGE_ERR OFFSET(8) NUMBITS(1) [],
390        SPURIOUS_ACK OFFSET(9) NUMBITS(1) [],
391        ARB_ERR OFFSET(10) NUMBITS(1) [],
392        HOST_GNT_ERR OFFSET(11) NUMBITS(1) [],
393    ],
394    pub(crate) ERR_ADDR [
395        ERR_ADDR OFFSET(0) NUMBITS(20) [],
396    ],
397    pub(crate) ECC_SINGLE_ERR_CNT [
398        ECC_SINGLE_ERR_CNT_0 OFFSET(0) NUMBITS(8) [],
399        ECC_SINGLE_ERR_CNT_1 OFFSET(8) NUMBITS(8) [],
400    ],
401    pub(crate) ECC_SINGLE_ERR_ADDR [
402        ECC_SINGLE_ERR_ADDR_0 OFFSET(0) NUMBITS(20) [],
403    ],
404    pub(crate) PHY_ALERT_CFG [
405        ALERT_ACK OFFSET(0) NUMBITS(1) [],
406        ALERT_TRIG OFFSET(1) NUMBITS(1) [],
407    ],
408    pub(crate) PHY_STATUS [
409        INIT_WIP OFFSET(0) NUMBITS(1) [],
410        PROG_NORMAL_AVAIL OFFSET(1) NUMBITS(1) [],
411        PROG_REPAIR_AVAIL OFFSET(2) NUMBITS(1) [],
412    ],
413    pub(crate) SCRATCH [
414        DATA OFFSET(0) NUMBITS(32) [],
415    ],
416    pub(crate) FIFO_LVL [
417        PROG OFFSET(0) NUMBITS(5) [],
418        RD OFFSET(8) NUMBITS(5) [],
419    ],
420    pub(crate) FIFO_RST [
421        EN OFFSET(0) NUMBITS(1) [],
422    ],
423    pub(crate) CURR_FIFO_LVL [
424        PROG OFFSET(0) NUMBITS(5) [],
425        RD OFFSET(8) NUMBITS(5) [],
426    ],
427];
428
429// End generated register constants for flash_ctrl
lowrisc/registers/flash_ctrl_regs.rs

lowrisc/registers/
flash_ctrl_regs.rs
