lowrisc/registers/
edn_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for edn.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/edn/data/edn.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alerts
15pub const EDN_PARAM_NUM_ALERTS: u32 = 2;
16/// Register width
17pub const EDN_PARAM_REG_WIDTH: u32 = 32;
18
19register_structs! {
20    pub EdnRegisters {
21        /// Interrupt State Register
22        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
23        /// Interrupt Enable Register
24        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
25        /// Interrupt Test Register
26        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
27        /// Alert Test Register
28        (0x000c => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
29        /// Register write enable for all control registers
30        (0x0010 => pub(crate) regwen: ReadWrite<u32, REGWEN::Register>),
31        /// EDN control register
32        (0x0014 => pub(crate) ctrl: ReadWrite<u32, CTRL::Register>),
33        /// EDN boot instantiate command register
34        (0x0018 => pub(crate) boot_ins_cmd: ReadWrite<u32, BOOT_INS_CMD::Register>),
35        /// EDN boot generate command register
36        (0x001c => pub(crate) boot_gen_cmd: ReadWrite<u32, BOOT_GEN_CMD::Register>),
37        /// EDN csrng app command request register
38        (0x0020 => pub(crate) sw_cmd_req: ReadWrite<u32, SW_CMD_REQ::Register>),
39        /// EDN command status register
40        (0x0024 => pub(crate) sw_cmd_sts: ReadWrite<u32, SW_CMD_STS::Register>),
41        /// EDN csrng reseed command register
42        (0x0028 => pub(crate) reseed_cmd: ReadWrite<u32, RESEED_CMD::Register>),
43        /// EDN csrng generate command register
44        (0x002c => pub(crate) generate_cmd: ReadWrite<u32, GENERATE_CMD::Register>),
45        /// EDN maximum number of requests between reseeds register
46        (0x0030 => pub(crate) max_num_reqs_between_reseeds: ReadWrite<u32, MAX_NUM_REQS_BETWEEN_RESEEDS::Register>),
47        /// Recoverable alert status register
48        (0x0034 => pub(crate) recov_alert_sts: ReadWrite<u32, RECOV_ALERT_STS::Register>),
49        /// Hardware detection of fatal error conditions status register
50        (0x0038 => pub(crate) err_code: ReadWrite<u32, ERR_CODE::Register>),
51        /// Test error conditions register
52        (0x003c => pub(crate) err_code_test: ReadWrite<u32, ERR_CODE_TEST::Register>),
53        /// Main state machine state observation register
54        (0x0040 => pub(crate) main_sm_state: ReadWrite<u32, MAIN_SM_STATE::Register>),
55        (0x0044 => @END),
56    }
57}
58
59register_bitfields![u32,
60    /// Common Interrupt Offsets
61    pub(crate) INTR [
62        EDN_CMD_REQ_DONE OFFSET(0) NUMBITS(1) [],
63        EDN_FATAL_ERR OFFSET(1) NUMBITS(1) [],
64    ],
65    pub(crate) ALERT_TEST [
66        RECOV_ALERT OFFSET(0) NUMBITS(1) [],
67        FATAL_ALERT OFFSET(1) NUMBITS(1) [],
68    ],
69    pub(crate) REGWEN [
70        REGWEN OFFSET(0) NUMBITS(1) [],
71    ],
72    pub(crate) CTRL [
73        EDN_ENABLE OFFSET(0) NUMBITS(4) [],
74        BOOT_REQ_MODE OFFSET(4) NUMBITS(4) [],
75        AUTO_REQ_MODE OFFSET(8) NUMBITS(4) [],
76        CMD_FIFO_RST OFFSET(12) NUMBITS(4) [],
77    ],
78    pub(crate) BOOT_INS_CMD [
79        BOOT_INS_CMD OFFSET(0) NUMBITS(32) [],
80    ],
81    pub(crate) BOOT_GEN_CMD [
82        BOOT_GEN_CMD OFFSET(0) NUMBITS(32) [],
83    ],
84    pub(crate) SW_CMD_REQ [
85        SW_CMD_REQ OFFSET(0) NUMBITS(32) [],
86    ],
87    pub(crate) SW_CMD_STS [
88        CMD_RDY OFFSET(0) NUMBITS(1) [],
89        CMD_STS OFFSET(1) NUMBITS(1) [],
90    ],
91    pub(crate) RESEED_CMD [
92        RESEED_CMD OFFSET(0) NUMBITS(32) [],
93    ],
94    pub(crate) GENERATE_CMD [
95        GENERATE_CMD OFFSET(0) NUMBITS(32) [],
96    ],
97    pub(crate) MAX_NUM_REQS_BETWEEN_RESEEDS [
98        MAX_NUM_REQS_BETWEEN_RESEEDS OFFSET(0) NUMBITS(32) [],
99    ],
100    pub(crate) RECOV_ALERT_STS [
101        EDN_ENABLE_FIELD_ALERT OFFSET(0) NUMBITS(1) [],
102        BOOT_REQ_MODE_FIELD_ALERT OFFSET(1) NUMBITS(1) [],
103        AUTO_REQ_MODE_FIELD_ALERT OFFSET(2) NUMBITS(1) [],
104        CMD_FIFO_RST_FIELD_ALERT OFFSET(3) NUMBITS(1) [],
105        EDN_BUS_CMP_ALERT OFFSET(12) NUMBITS(1) [],
106    ],
107    pub(crate) ERR_CODE [
108        SFIFO_RESCMD_ERR OFFSET(0) NUMBITS(1) [],
109        SFIFO_GENCMD_ERR OFFSET(1) NUMBITS(1) [],
110        SFIFO_OUTPUT_ERR OFFSET(2) NUMBITS(1) [],
111        EDN_ACK_SM_ERR OFFSET(20) NUMBITS(1) [],
112        EDN_MAIN_SM_ERR OFFSET(21) NUMBITS(1) [],
113        EDN_CNTR_ERR OFFSET(22) NUMBITS(1) [],
114        FIFO_WRITE_ERR OFFSET(28) NUMBITS(1) [],
115        FIFO_READ_ERR OFFSET(29) NUMBITS(1) [],
116        FIFO_STATE_ERR OFFSET(30) NUMBITS(1) [],
117    ],
118    pub(crate) ERR_CODE_TEST [
119        ERR_CODE_TEST OFFSET(0) NUMBITS(5) [],
120    ],
121    pub(crate) MAIN_SM_STATE [
122        MAIN_SM_STATE OFFSET(0) NUMBITS(9) [],
123    ],
124];
125
126// End generated register constants for edn
lowrisc/registers/edn_regs.rs

lowrisc/registers/
edn_regs.rs
