esp32/
rtc_cntl.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! Low Power Management driver.
6
7use kernel::platform::watchdog::WatchDog;
8use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable};
9use kernel::utilities::registers::{register_bitfields, register_structs, ReadWrite};
10use kernel::utilities::StaticRef;
11
12pub const RTC_CNTL_BASE: StaticRef<RtcCntlRegisters> =
13    unsafe { StaticRef::new(0x6000_8000 as *const RtcCntlRegisters) };
14
15register_structs! {
16    pub RtcCntlRegisters {
17        (0x000 => options0: ReadWrite<u32>),
18        (0x004 => slp_timer0: ReadWrite<u32>),
19        (0x008 => slp_timer1: ReadWrite<u32>),
20        (0x00C => time_update: ReadWrite<u32>),
21        (0x010 => time_low0: ReadWrite<u32>),
22        (0x014 => time_high0: ReadWrite<u32>),
23        (0x018 => state0: ReadWrite<u32>),
24        (0x01C => timer1: ReadWrite<u32>),
25        (0x020 => timer2: ReadWrite<u32>),
26        (0x024 => timer3: ReadWrite<u32>),
27        (0x028 => timer4: ReadWrite<u32>),
28        (0x02C => timer5: ReadWrite<u32>),
29        (0x030 => timer6: ReadWrite<u32>),
30        (0x034 => ana_conf: ReadWrite<u32>),
31        (0x038 => reset_state: ReadWrite<u32>),
32        (0x03C => wakeup_state: ReadWrite<u32>),
33        (0x040 => int_ena: ReadWrite<u32>),
34        (0x044 => int_raw: ReadWrite<u32>),
35        (0x048 => int_st: ReadWrite<u32>),
36        (0x04C => int_clr: ReadWrite<u32>),
37        (0x050 => store0: ReadWrite<u32>),
38        (0x054 => store1: ReadWrite<u32>),
39        (0x058 => store2: ReadWrite<u32>),
40        (0x05C => store3: ReadWrite<u32>),
41        (0x060 => ext_xtl_conf: ReadWrite<u32>),
42        (0x064 => ext_wakeup_conf: ReadWrite<u32>),
43        (0x068 => slp_reject_conf: ReadWrite<u32>),
44        (0x06C => cpu_period_conf: ReadWrite<u32>),
45        (0x070 => clk_conf: ReadWrite<u32, CLK_CONF::Register>),
46        (0x074 => slow_clk_conf: ReadWrite<u32>),
47        (0x078 => sdio_conf: ReadWrite<u32>),
48        (0x07C => bias_conf: ReadWrite<u32>),
49        (0x080 => vreg: ReadWrite<u32>),
50        (0x084 => pwc: ReadWrite<u32>),
51        (0x088 => dig_pwc: ReadWrite<u32>),
52        (0x08C => dig_iso: ReadWrite<u32>),
53        (0x090 => wdtconfig0: ReadWrite<u32, WDTCONFIG0::Register>),
54        (0x094 => wdtconfig1: ReadWrite<u32>),
55        (0x098 => wdtconfig2: ReadWrite<u32>),
56        (0x09C => wdtconfig3: ReadWrite<u32>),
57        (0x0A0 => wdtconfig4: ReadWrite<u32>),
58        (0x0A4 => wdtfeed: ReadWrite<u32>),
59        (0x0A8 => wdtprotect: ReadWrite<u32>),
60        (0x0AC => swd_conf: ReadWrite<u32, SWD_CONF::Register>),
61        (0x0B0 => swd_wprotect: ReadWrite<u32>),
62        (0x0B4 => sw_cpu_stall: ReadWrite<u32>),
63        (0x0B8 => store4: ReadWrite<u32>),
64        (0x0BC => store5: ReadWrite<u32>),
65        (0x0C0 => store6: ReadWrite<u32>),
66        (0x0C4 => store7: ReadWrite<u32>),
67        (0x0C8 => low_power_st: ReadWrite<u32>),
68        (0x0CC => daig0: ReadWrite<u32>),
69        (0x0D0 => pad_hold: ReadWrite<u32>),
70        (0x0D4 => _reserved0),
71        (0x10C => fib_sel: ReadWrite<u32, FIB_SEL::Register>),
72        (0x110 => @END),
73    }
74}
75
76register_bitfields![u32,
77    CLK_CONF [
78        DIG_FOSC_EN OFFSET(10) NUMBITS(1) [],
79    ],
80    WDTCONFIG0 [
81        CHIP_RESET_EN OFFSET(8) NUMBITS(1) [],
82        PAUSE_INSLEEP OFFSET(9) NUMBITS(1) [],
83        APPCPU_RESET_EN OFFSET(10) NUMBITS(1) [],
84        PROCPU_RESET_EN OFFSET(11) NUMBITS(1) [],
85        FLASHBOOT_MOD_EN OFFSET(12) NUMBITS(1) [],
86        SYS_RESET_LENGTH OFFSET(13) NUMBITS(3) [],
87        CPU_RESET_LENGTH OFFSET(16) NUMBITS(3) [],
88        STG3 OFFSET(19) NUMBITS(3) [],
89        STG2 OFFSET(22) NUMBITS(3) [],
90        STG1 OFFSET(25) NUMBITS(3) [],
91        STG0 OFFSET(28) NUMBITS(3) [],
92        EN OFFSET(31) NUMBITS(1) [],
93    ],
94    SWD_CONF [
95        AUTO_FEED OFFSET(31) NUMBITS(1) [],
96    ],
97    FIB_SEL [
98        FIB_SEL OFFSET(0) NUMBITS(3) [
99            GLITCH_RST = 1,
100            BOR_RST = 2,
101            SUPER_WDT_RST = 3,
102        ],
103    ],
104];
105
106pub struct RtcCntl {
107    registers: StaticRef<RtcCntlRegisters>,
108}
109
110impl RtcCntl {
111    pub const fn new(base: StaticRef<RtcCntlRegisters>) -> RtcCntl {
112        Self { registers: base }
113    }
114
115    /// Enable WDT config writes
116    fn enable_wdt_access(&self) {
117        self.registers.wdtprotect.set(0x50d8_3aa1);
118    }
119
120    /// Disable WDT config writes
121    fn disable_wdt_access(&self) {
122        self.registers.wdtprotect.set(0);
123    }
124
125    pub fn disable_wdt(&self) {
126        self.enable_wdt_access();
127
128        self.registers
129            .wdtconfig0
130            .modify(WDTCONFIG0::EN::CLEAR + WDTCONFIG0::FLASHBOOT_MOD_EN::CLEAR);
131        if self
132            .registers
133            .wdtconfig0
134            .is_set(WDTCONFIG0::FLASHBOOT_MOD_EN)
135        {
136            panic!("Can't disable RTC CNTL WDT");
137        }
138
139        self.disable_wdt_access();
140    }
141
142    /// Enable SW WDT config writes
143    fn enable_sw_wdt_access(&self) {
144        self.registers.swd_wprotect.set(0x8F1D_312A);
145    }
146
147    /// Disable SW WDT config writes
148    fn disable_sw_wdt_access(&self) {
149        self.registers.swd_wprotect.set(0);
150    }
151
152    pub fn disable_super_wdt(&self) {
153        self.registers.fib_sel.modify(FIB_SEL::FIB_SEL::BOR_RST);
154
155        self.enable_sw_wdt_access();
156        self.registers.swd_conf.modify(SWD_CONF::AUTO_FEED::SET);
157        self.disable_sw_wdt_access();
158    }
159
160    pub fn enable_fosc(&self) {
161        self.registers.clk_conf.modify(CLK_CONF::DIG_FOSC_EN::SET);
162    }
163}
164
165impl WatchDog for RtcCntl {
166    fn setup(&self) {}
167
168    fn tickle(&self) {}
169
170    fn suspend(&self) {}
171
172    fn resume(&self) {
173        self.tickle();
174    }
175}
esp32/rtc_cntl.rs

esp32/
rtc_cntl.rs
