earlgrey/registers/
ast_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for ast.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/top_earlgrey/ip/ast/data/ast.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of registers in the Array-B
15pub const AST_PARAM_NUM_REGS_B: u32 = 5;
16/// Number of USB valid beacon pulses for clock to re-calibrate
17pub const AST_PARAM_NUM_USB_BEACON_PULSES: u32 = 8;
18/// Register width
19pub const AST_PARAM_REG_WIDTH: u32 = 32;
20
21register_structs! {
22    pub AstRegisters {
23        /// AST Register 0 for OTP/ROM Write Testing
24        (0x0000 => pub(crate) rega0: ReadWrite<u32, REGA0::Register>),
25        /// AST 1 Register for OTP/ROM Write Testing
26        (0x0004 => pub(crate) rega1: ReadWrite<u32, REGA1::Register>),
27        /// AST 2 Register for OTP/ROM Write Testing
28        (0x0008 => pub(crate) rega2: ReadWrite<u32, REGA2::Register>),
29        /// AST 3 Register for OTP/ROM Write Testing
30        (0x000c => pub(crate) rega3: ReadWrite<u32, REGA3::Register>),
31        /// AST 4 Register for OTP/ROM Write Testing
32        (0x0010 => pub(crate) rega4: ReadWrite<u32, REGA4::Register>),
33        /// AST 5 Register for OTP/ROM Write Testing
34        (0x0014 => pub(crate) rega5: ReadWrite<u32, REGA5::Register>),
35        /// AST 6 Register for OTP/ROM Write Testing
36        (0x0018 => pub(crate) rega6: ReadWrite<u32, REGA6::Register>),
37        /// AST 7 Register for OTP/ROM Write Testing
38        (0x001c => pub(crate) rega7: ReadWrite<u32, REGA7::Register>),
39        /// AST 8 Register for OTP/ROM Write Testing
40        (0x0020 => pub(crate) rega8: ReadWrite<u32, REGA8::Register>),
41        /// AST 9 Register for OTP/ROM Write Testing
42        (0x0024 => pub(crate) rega9: ReadWrite<u32, REGA9::Register>),
43        /// AST 10 Register for OTP/ROM Write Testing
44        (0x0028 => pub(crate) rega10: ReadWrite<u32, REGA10::Register>),
45        /// AST 11 Register for OTP/ROM Write Testing
46        (0x002c => pub(crate) rega11: ReadWrite<u32, REGA11::Register>),
47        /// AST 13 Register for OTP/ROM Write Testing
48        (0x0030 => pub(crate) rega12: ReadWrite<u32, REGA12::Register>),
49        /// AST 13 Register for OTP/ROM Write Testing
50        (0x0034 => pub(crate) rega13: ReadWrite<u32, REGA13::Register>),
51        /// AST 14 Register for OTP/ROM Write Testing
52        (0x0038 => pub(crate) rega14: ReadWrite<u32, REGA14::Register>),
53        /// AST 15 Register for OTP/ROM Write Testing
54        (0x003c => pub(crate) rega15: ReadWrite<u32, REGA15::Register>),
55        /// AST 16 Register for OTP/ROM Write Testing
56        (0x0040 => pub(crate) rega16: ReadWrite<u32, REGA16::Register>),
57        /// AST 17 Register for OTP/ROM Write Testing
58        (0x0044 => pub(crate) rega17: ReadWrite<u32, REGA17::Register>),
59        /// AST 18 Register for OTP/ROM Write Testing
60        (0x0048 => pub(crate) rega18: ReadWrite<u32, REGA18::Register>),
61        /// AST 19 Register for OTP/ROM Write Testing
62        (0x004c => pub(crate) rega19: ReadWrite<u32, REGA19::Register>),
63        /// AST 20 Register for OTP/ROM Write Testing
64        (0x0050 => pub(crate) rega20: ReadWrite<u32, REGA20::Register>),
65        /// AST 21 Register for OTP/ROM Write Testing
66        (0x0054 => pub(crate) rega21: ReadWrite<u32, REGA21::Register>),
67        /// AST 22 Register for OTP/ROM Write Testing
68        (0x0058 => pub(crate) rega22: ReadWrite<u32, REGA22::Register>),
69        /// AST 23 Register for OTP/ROM Write Testing
70        (0x005c => pub(crate) rega23: ReadWrite<u32, REGA23::Register>),
71        /// AST 24 Register for OTP/ROM Write Testing
72        (0x0060 => pub(crate) rega24: ReadWrite<u32, REGA24::Register>),
73        /// AST 25 Register for OTP/ROM Write Testing
74        (0x0064 => pub(crate) rega25: ReadWrite<u32, REGA25::Register>),
75        /// AST 26 Register for OTP/ROM Write Testing
76        (0x0068 => pub(crate) rega26: ReadWrite<u32, REGA26::Register>),
77        /// AST 27 Register for OTP/ROM Write Testing
78        (0x006c => pub(crate) rega27: ReadWrite<u32, REGA27::Register>),
79        /// AST 28 Register for OTP/ROM Write Testing
80        (0x0070 => pub(crate) rega28: ReadWrite<u32, REGA28::Register>),
81        /// AST 29 Register for OTP/ROM Write Testing
82        (0x0074 => pub(crate) rega29: ReadWrite<u32, REGA29::Register>),
83        /// AST 30 Register for OTP/ROM Write Testing
84        (0x0078 => pub(crate) rega30: ReadWrite<u32, REGA30::Register>),
85        /// AST 31 Register for OTP/ROM Write Testing
86        (0x007c => pub(crate) rega31: ReadWrite<u32, REGA31::Register>),
87        /// AST 32 Register for OTP/ROM Write Testing
88        (0x0080 => pub(crate) rega32: ReadWrite<u32, REGA32::Register>),
89        /// AST 33 Register for OTP/ROM Write Testing
90        (0x0084 => pub(crate) rega33: ReadWrite<u32, REGA33::Register>),
91        /// AST 34 Register for OTP/ROM Write Testing
92        (0x0088 => pub(crate) rega34: ReadWrite<u32, REGA34::Register>),
93        /// AST 35 Register for OTP/ROM Write Testing
94        (0x008c => pub(crate) rega35: ReadWrite<u32, REGA35::Register>),
95        /// AST 36 Register for OTP/ROM Write Testing
96        (0x0090 => pub(crate) rega36: ReadWrite<u32, REGA36::Register>),
97        /// AST 37 Register for OTP/ROM Write Testing
98        (0x0094 => pub(crate) rega37: ReadWrite<u32, REGA37::Register>),
99        /// AST Last Register for OTP/ROM Write Testing
100        (0x0098 => pub(crate) regal: ReadWrite<u32, REGAL::Register>),
101        (0x009c => _reserved1),
102        /// AST Registers Array-B to set address space size
103        (0x0200 => pub(crate) regb: [ReadWrite<u32, REGB::Register>; 5]),
104        (0x0214 => @END),
105    }
106}
107
108register_bitfields![u32,
109    pub(crate) REGA0 [
110        REG32 OFFSET(0) NUMBITS(32) [],
111    ],
112    pub(crate) REGA1 [
113        REG32 OFFSET(0) NUMBITS(32) [],
114    ],
115    pub(crate) REGA2 [
116        REG32 OFFSET(0) NUMBITS(32) [],
117    ],
118    pub(crate) REGA3 [
119        REG32 OFFSET(0) NUMBITS(32) [],
120    ],
121    pub(crate) REGA4 [
122        REG32 OFFSET(0) NUMBITS(32) [],
123    ],
124    pub(crate) REGA5 [
125        REG32 OFFSET(0) NUMBITS(32) [],
126    ],
127    pub(crate) REGA6 [
128        REG32 OFFSET(0) NUMBITS(32) [],
129    ],
130    pub(crate) REGA7 [
131        REG32 OFFSET(0) NUMBITS(32) [],
132    ],
133    pub(crate) REGA8 [
134        REG32 OFFSET(0) NUMBITS(32) [],
135    ],
136    pub(crate) REGA9 [
137        REG32 OFFSET(0) NUMBITS(32) [],
138    ],
139    pub(crate) REGA10 [
140        REG32 OFFSET(0) NUMBITS(32) [],
141    ],
142    pub(crate) REGA11 [
143        REG32 OFFSET(0) NUMBITS(32) [],
144    ],
145    pub(crate) REGA12 [
146        REG32 OFFSET(0) NUMBITS(32) [],
147    ],
148    pub(crate) REGA13 [
149        REG32 OFFSET(0) NUMBITS(32) [],
150    ],
151    pub(crate) REGA14 [
152        REG32 OFFSET(0) NUMBITS(32) [],
153    ],
154    pub(crate) REGA15 [
155        REG32 OFFSET(0) NUMBITS(32) [],
156    ],
157    pub(crate) REGA16 [
158        REG32 OFFSET(0) NUMBITS(32) [],
159    ],
160    pub(crate) REGA17 [
161        REG32 OFFSET(0) NUMBITS(32) [],
162    ],
163    pub(crate) REGA18 [
164        REG32 OFFSET(0) NUMBITS(32) [],
165    ],
166    pub(crate) REGA19 [
167        REG32 OFFSET(0) NUMBITS(32) [],
168    ],
169    pub(crate) REGA20 [
170        REG32 OFFSET(0) NUMBITS(32) [],
171    ],
172    pub(crate) REGA21 [
173        REG32 OFFSET(0) NUMBITS(32) [],
174    ],
175    pub(crate) REGA22 [
176        REG32 OFFSET(0) NUMBITS(32) [],
177    ],
178    pub(crate) REGA23 [
179        REG32 OFFSET(0) NUMBITS(32) [],
180    ],
181    pub(crate) REGA24 [
182        REG32 OFFSET(0) NUMBITS(32) [],
183    ],
184    pub(crate) REGA25 [
185        REG32 OFFSET(0) NUMBITS(32) [],
186    ],
187    pub(crate) REGA26 [
188        REG32 OFFSET(0) NUMBITS(32) [],
189    ],
190    pub(crate) REGA27 [
191        REG32 OFFSET(0) NUMBITS(32) [],
192    ],
193    pub(crate) REGA28 [
194        REG32 OFFSET(0) NUMBITS(32) [],
195    ],
196    pub(crate) REGA29 [
197        REG32 OFFSET(0) NUMBITS(32) [],
198    ],
199    pub(crate) REGA30 [
200        REG32 OFFSET(0) NUMBITS(32) [],
201    ],
202    pub(crate) REGA31 [
203        REG32 OFFSET(0) NUMBITS(32) [],
204    ],
205    pub(crate) REGA32 [
206        REG32 OFFSET(0) NUMBITS(32) [],
207    ],
208    pub(crate) REGA33 [
209        REG32 OFFSET(0) NUMBITS(32) [],
210    ],
211    pub(crate) REGA34 [
212        REG32 OFFSET(0) NUMBITS(32) [],
213    ],
214    pub(crate) REGA35 [
215        REG32 OFFSET(0) NUMBITS(32) [],
216    ],
217    pub(crate) REGA36 [
218        REG32 OFFSET(0) NUMBITS(32) [],
219    ],
220    pub(crate) REGA37 [
221        REG32 OFFSET(0) NUMBITS(32) [],
222    ],
223    pub(crate) REGAL [
224        REG32 OFFSET(0) NUMBITS(32) [],
225    ],
226    pub(crate) REGB [
227        REG32_0 OFFSET(0) NUMBITS(32) [],
228    ],
229];
230
231// End generated register constants for ast
earlgrey/registers/ast_regs.rs

earlgrey/registers/
ast_regs.rs
