apollo3/
mcuctrl.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5//! MCU Control driver.
6
7use kernel::debug;
8use kernel::utilities::registers::interfaces::{ReadWriteable, Readable};
9use kernel::utilities::registers::{register_bitfields, register_structs, ReadWrite};
10use kernel::utilities::StaticRef;
11
12const MCUCTRL_BASE: StaticRef<McuCtrlRegisters> =
13    unsafe { StaticRef::new(0x4002_0000 as *const McuCtrlRegisters) };
14
15register_structs! {
16    pub McuCtrlRegisters {
17        (0x000 => chippn: ReadWrite<u32>),
18        (0x004 => chipid0: ReadWrite<u32>),
19        (0x008 => chipid1: ReadWrite<u32>),
20        (0x00c => chiprev: ReadWrite<u32, CHIPREV::Register>),
21        (0x010 => vendorid: ReadWrite<u32>),
22        (0x014 => sku: ReadWrite<u32>),
23        (0x018 => featureenable: ReadWrite<u32, FEATUREENABLE::Register>),
24        (0x01C => _reserved0),
25        (0x020 => debugger: ReadWrite<u32>),
26        (0x024 => _reserved1),
27        (0x104 => adcpwrdly: ReadWrite<u32>),
28        (0x108 => _reserved2),
29        (0x10C => adccal: ReadWrite<u32>),
30        (0x110 => adcbattload: ReadWrite<u32>),
31        (0x114 => _reserved3),
32        (0x118 => adctrim: ReadWrite<u32>),
33        (0x11C => adcrefcomp: ReadWrite<u32>),
34        (0x120 => xtalctrl: ReadWrite<u32>),
35        (0x124 => xtalgenctrl: ReadWrite<u32>),
36        (0x128 => _reserved4),
37        (0x198 => miscctrl: ReadWrite<u32, MISCCTRL::Register>),
38        (0x19C => _reserved5),
39        (0x1A0 => bootloader: ReadWrite<u32>),
40        (0x1A4 => shadowvalid: ReadWrite<u32>),
41        (0x1A8 => _reserved6),
42        (0x1B0 => scratch0: ReadWrite<u32>),
43        (0x1B4 => scratch1: ReadWrite<u32>),
44        (0x1B8 => _reserved7),
45        (0x1C0 => icodefaultaddr: ReadWrite<u32>),
46        (0x1C4 => dcodefaultaddr: ReadWrite<u32>),
47        (0x1C8 => sysfaultaddr: ReadWrite<u32>),
48        (0x1CC => faultstatus: ReadWrite<u32>),
49        (0x1D0 => faultcaptureen: ReadWrite<u32>),
50        (0x1D4 => _reserved8),
51        (0x200 => dbgr1: ReadWrite<u32>),
52        (0x204 => dbgr2: ReadWrite<u32>),
53        (0x208 => _reserved9),
54        (0x220 => pmuenable: ReadWrite<u32>),
55        (0x224 => _reserved10),
56        (0x250 => tpiuctrl: ReadWrite<u32>),
57        (0x254 => _reserved11),
58        (0x264 => otapointer: ReadWrite<u32>),
59        (0x268 => _reserved12),
60        (0x284 => srammode: ReadWrite<u32>),
61        (0x288 => _reserved13),
62        (0x348 => kextclksel: ReadWrite<u32>),
63        (0x34C => _reserved14),
64        (0x358 => simobuck3: ReadWrite<u32>),
65        (0x35C => simobuck4: ReadWrite<u32>),
66        (0x360 => _reserved15),
67        (0x368 => blebuck2: ReadWrite<u32, BLEBUCK2::Register>),
68        (0x36C => _reserved16),
69        (0x3A0 => flashwprot0: ReadWrite<u32>),
70        (0x3A4 => flashwprot1: ReadWrite<u32>),
71        (0x3A8 => _reserved17),
72        (0x3B0 => flashrprot0: ReadWrite<u32>),
73        (0x3B4 => flashrprot1: ReadWrite<u32>),
74        (0x3B8 => _reserved18),
75        (0x3C0 => dmasramwriteprotect0: ReadWrite<u32>),
76        (0x3C4 => dmasramwriteprotect1: ReadWrite<u32>),
77        (0x3C8 => _reserved19),
78        (0x3D0 => dmasramreadprotect0: ReadWrite<u32>),
79        (0x3D4 => dmasramreadprotect1: ReadWrite<u32>),
80        (0x3D8 => @END),
81    }
82}
83
84register_bitfields![u32,
85    CHIPREV [
86        REVMIN OFFSET(0) NUMBITS(3) [],
87        REVMAJ OFFSET(4) NUMBITS(3) [],
88        SIPART OFFSET(8) NUMBITS(12) []
89    ],
90    FEATUREENABLE [
91        BLEREQ OFFSET(0) NUMBITS(1) [],
92        BLEACK OFFSET(1) NUMBITS(1) [],
93        BLEAVAIL OFFSET(2) NUMBITS(1) [],
94        BURSTREQ OFFSET(4) NUMBITS(1) [],
95        BURSTSTACK OFFSET(5) NUMBITS(1) [],
96        BURSTAVAIL OFFSET(6) NUMBITS(1) []
97    ],
98    MISCCTRL [
99        BLE_RESETN OFFSET(5) NUMBITS(1) []
100    ],
101    BLEBUCK2 [
102        BLEBUCKTONLOWTRIM OFFSET(0) NUMBITS(6) [],
103        BLEBUCKTONHITRIM OFFSET(6) NUMBITS(6) [],
104        BLEBUCKTOND2ATRIM OFFSET(12) NUMBITS(6) []
105    ]
106];
107
108pub struct McuCtrl {
109    registers: StaticRef<McuCtrlRegisters>,
110}
111
112impl McuCtrl {
113    pub const fn new() -> McuCtrl {
114        McuCtrl {
115            registers: MCUCTRL_BASE,
116        }
117    }
118
119    pub fn print_chip_revision(&self) {
120        let regs = self.registers;
121
122        let chiprev = regs.chiprev.extract();
123
124        // We currenlty don't act on this (we probably should)
125        if chiprev.read(CHIPREV::REVMAJ) == 0x2 {
126            debug!("Apollo3 chip revision: B");
127        } else if chiprev.read(CHIPREV::REVMAJ) == 0x1 {
128            if chiprev.read(CHIPREV::REVMIN) == 0x2 {
129                debug!("Apollo3 chip revision: A rev1");
130            } else if chiprev.read(CHIPREV::REVMIN) == 0x1 {
131                debug!("Apollo3 chip revision: A rev0");
132            }
133        }
134    }
135
136    pub fn disable_ble(&self) {
137        self.registers
138            .featureenable
139            .modify(FEATUREENABLE::BLEREQ::CLEAR);
140    }
141
142    pub fn enable_ble(&self) {
143        let regs = self.registers;
144
145        regs.blebuck2
146            .modify(BLEBUCK2::BLEBUCKTONHITRIM.val(0x19) + BLEBUCK2::BLEBUCKTONLOWTRIM.val(0xC));
147
148        regs.featureenable.modify(FEATUREENABLE::BLEREQ::SET);
149
150        while !regs.featureenable.is_set(FEATUREENABLE::BLEREQ)
151            && regs.featureenable.is_set(FEATUREENABLE::BLEACK)
152            && regs.featureenable.is_set(FEATUREENABLE::BLEAVAIL)
153        {}
154    }
155
156    pub fn reset_ble(&self) {
157        let regs = self.registers;
158
159        regs.miscctrl.modify(MISCCTRL::BLE_RESETN::SET);
160    }
161}
apollo3/mcuctrl.rs

apollo3/
mcuctrl.rs
